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Initial commit: component/bq25750rrvr

Ray ·6f57c512f3 ·1mo ago
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README.mdadded+74
@@ -0,0 +1,74 @@+# BQ25750RRVR++**Texas Instruments** · Battery Management · VQFN-36-EP(6x5)++BQ25750RRVR from Texas Instruments, in a VQFN-36-EP(6x5). Pinout and pin descriptions extracted from the manufacturer datasheet by ds2sf; symbol, footprint, and 3D from KiCad-official CAD.++## Pinout++| Pin | Name | Type | Function |+|---|---|---|---|+| 1 | SCL | input | I2C interface clock input; connect through 10kΩ resistor to logic rail for standard I2C protocol communication. |+| 2 | SDA | bidirectional | I2C interface data line; open-drain bidirectional, connect through 10kΩ resistor to logic rail for standard I2C protocol communication. |+| 3 | INT | output | Open-drain interrupt output; low-active 256μs pulse notifies host of device state change or fault, connect through 10kΩ pullup resistor. |+| 4 | STAT1 | output | Open-drain charge status output; indicates charging operation with STAT2, connect through 10kΩ pullup resistor to power rail. |+| 5 | STAT2 | output | Open-drain charge status output; indicates charging operation with STAT1, connect through 10kΩ pullup resistor to power rail. |+| 6 | PG | output | Open-drain low-active power good status indicator; LOW indicates input source valid when VAC is within ACUV/ACOV window, connect through 10kΩ pullup. |+| 7 | CE | bidirectional | Low-active charge enable input pin; pull to low to enable charging when EN_CHG=1, must be pulled high or low, do not leave floating. |+| 8 | TS | input | Temperature sensing voltage input; connect negative temperature coefficient thermistor via resistive divider from REGN to PGND to program temperature window. |+| 9 | ICHG | input | Charge current limit setting input; connect programming resistor to PGND to set ICHG = KICHG/RICHG, pull to PGND if unused. |+| 10 | ILIM_HIZ | input | Input current limit and high-Z mode control pin; programming resistor to PGND sets input current limit ILIM = KILIM/RILIM, or pull high to force high-impedance mode. |+| 11 | FBG | input | Voltage feedback divider return; connect to bottom of battery feedback resistor, driven to PGND during charging, high-impedance when input outside ACUV/ACOV window. |+| 12 | FB | input | Charge voltage analog feedback regulation input; connect resistor divider from battery terminals to set output battery regulation voltage. |+| 13 | SRN | input | Charge current sense resistor negative input; place 0.47μF ceramic capacitor between SRN and SRP for differential filtering and optional 0.1μF to PGND for common-mode filtering. |+| 14 | SRP | input | Charge current sense resistor positive input; place 0.47μF ceramic capacitor between SRN and SRP for differential filtering and 0.1μF ceramic capacitor to PGND for common-mode filtering. |+| 15 | BATDRV | output | N-channel battery FET gate drive output; connect directly to BATFET gate, drives 10V relative to BATSRC when input within ACUV/ACOV window. |+| 16 | BATSRC | power_in | N-channel battery FET source input; connect directly to BATFET source for common-source configuration. |+| 17 | PGND | power_in | Power ground connection; connect directly to power ground plane. |+| 18 | SW2 | passive | Boost-side half-bridge switch node; connect inductor between SW1 and SW2 for buck-boost conversion. |+| 19 | HIDRV2 | output | Boost-side high-side gate driver output; connect to boost high-side N-channel MOSFET gate. |+| 20 | BTST2 | power_in | Boost-side high-side gate driver power supply node; connect capacitor between BTST2 and SW2 to provide bias for high-side MOSFET gate driver. |+| 21 | LODRV2 | output | Boost-side low-side gate driver output; connect to boost low-side N-channel MOSFET gate. |+| 22 | PGND | power_in | Power ground loop connection; high-current ground connection for low-side gate driver, connect to ground plane. |+| 23 | DRV_SUP | power_in | Gate driver supply power input; connect 4.7μF ceramic capacitor to PGND, accepts 4V to 12V external supply for FET gate driving or use with REGN for 5V operation. |+| 24 | REGN | power_in | Charger internal linear regulator output; 5V LDO output nominally 4.8-5.2V, connect 4.7μF ceramic capacitor to PGND, can supply gate driver circuits up to 70mA. |+| 25 | LODRV1 | output | Buck-side low-side gate driver output; connect to buck low-side N-channel MOSFET gate. |+| 26 | BTST1 | power_in | Buck-side high-side gate driver power supply node; connect capacitor between BTST1 and SW1 to provide bias for high-side MOSFET gate driver. |+| 27 | HIDRV1 | output | Buck-side high-side gate driver output; connect to buck high-side N-channel MOSFET gate. |+| 28 | SW1 | passive | Buck-side half-bridge switch node; connect inductor between SW1 and SW2 for buck-boost conversion. |+| 29 | ACN | input | Adapter current sense resistor negative input; place 0.47μF ceramic capacitor between ACN and ACP for differential filtering and optional 0.1μF to PGND for common-mode filtering. |+| 30 | ACP | input | Adapter current sense resistor positive input; place 0.47μF ceramic capacitor between ACN and ACP for differential filtering and 0.1μF ceramic capacitor to PGND for common-mode filtering. |+| 31 | ACDRV | output | N-channel input FET gate drive output; drive ACFET gate to 10V when input within ACUV/ACOV window, pull to PGND to turn off FET, connect 15V Zener diode from ACDRV to ACFET source. |+| 32 | SYS | input | System voltage detect point; voltage sensing point for system rail, regulated to VSYS_REV in reverse mode when input voltage outside operating window. |+| 33 | VAC | power_in | Input voltage detect and power supply node; 4.2V to 70V input bias for IC operation, connect 1μF capacitor between pin and PGND. |+| 34 | ACUV | input | Input undervoltage comparator input; connect resistive divider between VAC and PGND to program input undervooltage protection threshold, pull to VAC if unused. |+| 35 | ACOV | input | Input overvoltage comparator input; connect resistive divider between VAC and PGND to program input overvoltage protection threshold, pull to PGND if unused. |+| 36 | FSW_SYNC | input | Switch frequency and sync input; connect resistor to PGND to program switching frequency from 200kHz to 600kHz, or input external clock from 200kHz to 600kHz for synchronization. |+| 37 | Thermal Pad | passive | Exposed thermal pad beneath IC; solder to board and connect via thermal vias to PGND and power ground plane for heat dissipation and thermal performance. |++## Key specifications++| Parameter | Value |+|---|---|+| Manufacturer | Texas Instruments |+| Package | VQFN-36-EP(6x5) |+| Category | Power Management (PMIC) |+| Pins | 37 |++## CAD (KiCad official)++- Symbol: `BQ25750RRVR`+- Footprint: `Package_DFN_QFN:QFN-36-1EP_5x6mm_P0.5mm_EP3.6x4.6mm`+- 3D model: VQFN-36-EP(6x5) (KiCad packages3D, STEP)+- 3D model files: `bq25750rrvr-etched.step` / `bq25750rrvr-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `bq25750rrvr.step` / `bq25750rrvr.glb` are the bare package body.++## Provenance++Data extracted from the manufacturer datasheet, not a distributor listing:++- **Datasheet:** [Texas Instruments datasheet](https://www.ti.com/cn/lit/gpn/bq25750) (81 pp, sha256 `ea96ae5a890971ff`, retrieved 2026-09-23, tier: lcsc)+- **Datasheet language:** Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.+- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.2`, primary `claude-haiku-4-5-20251001` (text), consensus `claude-sonnet-5` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.+- **CAD:** KiCad official libraries (CC-BY-SA 4.0).++[Datasheet PDF](docs/bq25750rrvr-datasheet.pdf)
page.jsonadded+317
@@ -0,0 +1,317 @@+{+  "slug": "bq25750rrvr",+  "version": "0.1.0",+  "type": "component",+  "description": "Texas Instruments Battery Management, VQFN-36-EP(6x5). Datasheet-verified pinout, KiCad symbol/footprint/3D.",+  "tags": [+    "component",+    "power management (pmic)",+    "bq25750rrvr",+    "factory-2.0.0",+    "extractor-text"+  ],+  "dependencies": {},+  "hero": {+    "type": "image",+    "path": "docs/hero.png"+  },+  "files": [+    "page.json",+    "README.md",+    "bq25750rrvr.kicad_sym",+    "bq25750rrvr.kicad_mod",+    "bq25750rrvr.glb",+    "bq25750rrvr.step",+    "bq25750rrvr.lbr",+    "docs/hero.png",+    "docs/bq25750rrvr-datasheet.pdf",+    "viewers/symbol.html",+    "viewers/footprint.html"+  ],+  "component": {+    "mpn": "BQ25750RRVR",+    "manufacturer": "Texas Instruments",+    "package": "VQFN-36-EP(6x5)",+    "pin_count": 37,+    "category": "Power Management (PMIC)",+    "subcategory": "Battery Management",+    "datasheet": "https://www.ti.com/cn/lit/gpn/bq25750",+    "parts": {+      "symbol": "bq25750rrvr.kicad_sym",+      "footprint": "bq25750rrvr.kicad_mod",+      "model_3d": "bq25750rrvr-etched.glb",+      "model_3d_plain": "bq25750rrvr.glb",+      "model_3d_step": "bq25750rrvr-etched.step",+      "model_3d_step_plain": "bq25750rrvr.step",+      "lbr": "bq25750rrvr.lbr"+    },+    "distributor_links": {+      "lcsc": "C22427288"+    },+    "pins": [+      {+        "number": "1",+        "name": "SCL",+        "type": "input",+        "description": "I2C interface clock input; connect through 10kΩ resistor to logic rail for standard I2C protocol communication."+      },+      {+        "number": "2",+        "name": "SDA",+        "type": "bidirectional",+        "description": "I2C interface data line; open-drain bidirectional, connect through 10kΩ resistor to logic rail for standard I2C protocol communication."+      },+      {+        "number": "3",+        "name": "INT",+        "type": "output",+        "description": "Open-drain interrupt output; low-active 256μs pulse notifies host of device state change or fault, connect through 10kΩ pullup resistor."+      },+      {+        "number": "4",+        "name": "STAT1",+        "type": "output",+        "description": "Open-drain charge status output; indicates charging operation with STAT2, connect through 10kΩ pullup resistor to power rail."+      },+      {+        "number": "5",+        "name": "STAT2",+        "type": "output",+        "description": "Open-drain charge status output; indicates charging operation with STAT1, connect through 10kΩ pullup resistor to power rail."+      },+      {+        "number": "6",+        "name": "PG",+        "type": "output",+        "description": "Open-drain low-active power good status indicator; LOW indicates input source valid when VAC is within ACUV/ACOV window, connect through 10kΩ pullup."+      },+      {+        "number": "7",+        "name": "CE",+        "type": "bidirectional",+        "description": "Low-active charge enable input pin; pull to low to enable charging when EN_CHG=1, must be pulled high or low, do not leave floating."+      },+      {+        "number": "8",+        "name": "TS",+        "type": "input",+        "description": "Temperature sensing voltage input; connect negative temperature coefficient thermistor via resistive divider from REGN to PGND to program temperature window."+      },+      {+        "number": "9",+        "name": "ICHG",+        "type": "input",+        "description": "Charge current limit setting input; connect programming resistor to PGND to set ICHG = KICHG/RICHG, pull to PGND if unused."+      },+      {+        "number": "10",+        "name": "ILIM_HIZ",+        "type": "input",+        "description": "Input current limit and high-Z mode control pin; programming resistor to PGND sets input current limit ILIM = KILIM/RILIM, or pull high to force high-impedance mode."+      },+      {+        "number": "11",+        "name": "FBG",+        "type": "input",+        "description": "Voltage feedback divider return; connect to bottom of battery feedback resistor, driven to PGND during charging, high-impedance when input outside ACUV/ACOV window."+      },+      {+        "number": "12",+        "name": "FB",+        "type": "input",+        "description": "Charge voltage analog feedback regulation input; connect resistor divider from battery terminals to set output battery regulation voltage."+      },+      {+        "number": "13",+        "name": "SRN",+        "type": "input",+        "description": "Charge current sense resistor negative input; place 0.47μF ceramic capacitor between SRN and SRP for differential filtering and optional 0.1μF to PGND for common-mode filtering."+      },+      {+        "number": "14",+        "name": "SRP",+        "type": "input",+        "description": "Charge current sense resistor positive input; place 0.47μF ceramic capacitor between SRN and SRP for differential filtering and 0.1μF ceramic capacitor to PGND for common-mode filtering."+      },+      {+        "number": "15",+        "name": "BATDRV",+        "type": "output",+        "description": "N-channel battery FET gate drive output; connect directly to BATFET gate, drives 10V relative to BATSRC when input within ACUV/ACOV window."+      },+      {+        "number": "16",+        "name": "BATSRC",+        "type": "power_in",+        "description": "N-channel battery FET source input; connect directly to BATFET source for common-source configuration."+      },+      {+        "number": "17",+        "name": "PGND",+        "type": "power_in",+        "description": "Power ground connection; connect directly to power ground plane."+      },+      {+        "number": "18",+        "name": "SW2",+        "type": "passive",+        "description": "Boost-side half-bridge switch node; connect inductor between SW1 and SW2 for buck-boost conversion."+      },+      {+        "number": "19",+        "name": "HIDRV2",+        "type": "output",+        "description": "Boost-side high-side gate driver output; connect to boost high-side N-channel MOSFET gate."+      },+      {+        "number": "20",+        "name": "BTST2",+        "type": "power_in",+        "description": "Boost-side high-side gate driver power supply node; connect capacitor between BTST2 and SW2 to provide bias for high-side MOSFET gate driver."+      },+      {+        "number": "21",+        "name": "LODRV2",+        "type": "output",+        "description": "Boost-side low-side gate driver output; connect to boost low-side N-channel MOSFET gate."+      },+      {+        "number": "22",+        "name": "PGND",+        "type": "power_in",+        "description": "Power ground loop connection; high-current ground connection for low-side gate driver, connect to ground plane."+      },+      {+        "number": "23",+        "name": "DRV_SUP",+        "type": "power_in",+        "description": "Gate driver supply power input; connect 4.7μF ceramic capacitor to PGND, accepts 4V to 12V external supply for FET gate driving or use with REGN for 5V operation."+      },+      {+        "number": "24",+        "name": "REGN",+        "type": "power_in",+        "description": "Charger internal linear regulator output; 5V LDO output nominally 4.8-5.2V, connect 4.7μF ceramic capacitor to PGND, can supply gate driver circuits up to 70mA."+      },+      {+        "number": "25",+        "name": "LODRV1",+        "type": "output",+        "description": "Buck-side low-side gate driver output; connect to buck low-side N-channel MOSFET gate."+      },+      {+        "number": "26",+        "name": "BTST1",+        "type": "power_in",+        "description": "Buck-side high-side gate driver power supply node; connect capacitor between BTST1 and SW1 to provide bias for high-side MOSFET gate driver."+      },+      {+        "number": "27",+        "name": "HIDRV1",+        "type": "output",+        "description": "Buck-side high-side gate driver output; connect to buck high-side N-channel MOSFET gate."+      },+      {+        "number": "28",+        "name": "SW1",+        "type": "passive",+        "description": "Buck-side half-bridge switch node; connect inductor between SW1 and SW2 for buck-boost conversion."+      },+      {+        "number": "29",+        "name": "ACN",+        "type": "input",+        "description": "Adapter current sense resistor negative input; place 0.47μF ceramic capacitor between ACN and ACP for differential filtering and optional 0.1μF to PGND for common-mode filtering."+      },+      {+        "number": "30",+        "name": "ACP",+        "type": "input",+        "description": "Adapter current sense resistor positive input; place 0.47μF ceramic capacitor between ACN and ACP for differential filtering and 0.1μF ceramic capacitor to PGND for common-mode filtering."+      },+      {+        "number": "31",+        "name": "ACDRV",+        "type": "output",+        "description": "N-channel input FET gate drive output; drive ACFET gate to 10V when input within ACUV/ACOV window, pull to PGND to turn off FET, connect 15V Zener diode from ACDRV to ACFET source."+      },+      {+        "number": "32",+        "name": "SYS",+        "type": "input",+        "description": "System voltage detect point; voltage sensing point for system rail, regulated to VSYS_REV in reverse mode when input voltage outside operating window."+      },+      {+        "number": "33",+        "name": "VAC",+        "type": "power_in",+        "description": "Input voltage detect and power supply node; 4.2V to 70V input bias for IC operation, connect 1μF capacitor between pin and PGND."+      },+      {+        "number": "34",+        "name": "ACUV",+        "type": "input",+        "description": "Input undervoltage comparator input; connect resistive divider between VAC and PGND to program input undervooltage protection threshold, pull to VAC if unused."+      },+      {+        "number": "35",+        "name": "ACOV",+        "type": "input",+        "description": "Input overvoltage comparator input; connect resistive divider between VAC and PGND to program input overvoltage protection threshold, pull to PGND if unused."+      },+      {+        "number": "36",+        "name": "FSW_SYNC",+        "type": "input",+        "description": "Switch frequency and sync input; connect resistor to PGND to program switching frequency from 200kHz to 600kHz, or input external clock from 200kHz to 600kHz for synchronization."+      },+      {+        "number": "37",+        "name": "Thermal Pad",+        "type": "passive",+        "description": "Exposed thermal pad beneath IC; solder to board and connect via thermal vias to PGND and power ground plane for heat dissipation and thermal performance."+      }+    ],+    "provenance": {+      "extractor": "extract_pins 0.2",+      "factory_chain": {+        "factory": "2.0.0",+        "extractor": "extract_pins 0.2",+        "primary_model": "claude-haiku-4-5-20251001",+        "primary_mode": "text",+        "consensus_model": "claude-sonnet-5",+        "consensus": "agreed",+        "guards": "pin_guards 0.1: passed",+        "guard_notes": [+          "extractor flagged: BATSRC and REGN pins classified as power_in despite being signal processing outputs - they should te"+        ],+        "pages_sent": 81,+        "cost_usd": 0.9812,+        "at": "2026-09-23T15:24:05"+      },+      "datasheet": {+        "url": "https://www.ti.com/cn/lit/gpn/bq25750",+        "pages": 81,+        "sha256": "ea96ae5a890971ff",+        "source_tier": "lcsc"+      },+      "cad": "KiCad official (CC-BY-SA 4.0)",+      "pins": {+        "total": 37,+        "described": 37,+        "cites_pages": true,+        "refuses_to_fabricate": true+      }+    },+    "viewers": {+      "symbol": "viewers/symbol.html",+      "footprint": "viewers/footprint.html"+    }+  },+  "visibility": "public",+  "org": "adom",+  "author": {+    "name": "Ray",+    "email": "[email protected]"+  }+}\ No newline at end of file