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Contents

Pinout
Key specifications
CAD (KiCad official)
Provenance

README

markdown

BQ25750RRVR

Texas Instruments · Battery Management · VQFN-36-EP(6x5)

BQ25750RRVR from Texas Instruments, in a VQFN-36-EP(6x5). Pinout and pin descriptions extracted from the manufacturer datasheet by ds2sf; symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin	Name	Type	Function
1	SCL	input	I2C interface clock input; connect through 10kΩ resistor to logic rail for standard I2C protocol communication.
2	SDA	bidirectional	I2C interface data line; open-drain bidirectional, connect through 10kΩ resistor to logic rail for standard I2C protocol communication.
3	INT	output	Open-drain interrupt output; low-active 256μs pulse notifies host of device state change or fault, connect through 10kΩ pullup resistor.
4	STAT1	output	Open-drain charge status output; indicates charging operation with STAT2, connect through 10kΩ pullup resistor to power rail.
5	STAT2	output	Open-drain charge status output; indicates charging operation with STAT1, connect through 10kΩ pullup resistor to power rail.
6	PG	output	Open-drain low-active power good status indicator; LOW indicates input source valid when VAC is within ACUV/ACOV window, connect through 10kΩ pullup.
7	CE	bidirectional	Low-active charge enable input pin; pull to low to enable charging when EN_CHG=1, must be pulled high or low, do not leave floating.
8	TS	input	Temperature sensing voltage input; connect negative temperature coefficient thermistor via resistive divider from REGN to PGND to program temperature window.
9	ICHG	input	Charge current limit setting input; connect programming resistor to PGND to set ICHG = KICHG/RICHG, pull to PGND if unused.
10	ILIM_HIZ	input	Input current limit and high-Z mode control pin; programming resistor to PGND sets input current limit ILIM = KILIM/RILIM, or pull high to force high-impedance mode.
11	FBG	input	Voltage feedback divider return; connect to bottom of battery feedback resistor, driven to PGND during charging, high-impedance when input outside ACUV/ACOV window.
12	FB	input	Charge voltage analog feedback regulation input; connect resistor divider from battery terminals to set output battery regulation voltage.
13	SRN	input	Charge current sense resistor negative input; place 0.47μF ceramic capacitor between SRN and SRP for differential filtering and optional 0.1μF to PGND for common-mode filtering.
14	SRP	input	Charge current sense resistor positive input; place 0.47μF ceramic capacitor between SRN and SRP for differential filtering and 0.1μF ceramic capacitor to PGND for common-mode filtering.
15	BATDRV	output	N-channel battery FET gate drive output; connect directly to BATFET gate, drives 10V relative to BATSRC when input within ACUV/ACOV window.
16	BATSRC	power_in	N-channel battery FET source input; connect directly to BATFET source for common-source configuration.
17	PGND	power_in	Power ground connection; connect directly to power ground plane.
18	SW2	passive	Boost-side half-bridge switch node; connect inductor between SW1 and SW2 for buck-boost conversion.
19	HIDRV2	output	Boost-side high-side gate driver output; connect to boost high-side N-channel MOSFET gate.
20	BTST2	power_in	Boost-side high-side gate driver power supply node; connect capacitor between BTST2 and SW2 to provide bias for high-side MOSFET gate driver.
21	LODRV2	output	Boost-side low-side gate driver output; connect to boost low-side N-channel MOSFET gate.
22	PGND	power_in	Power ground loop connection; high-current ground connection for low-side gate driver, connect to ground plane.
23	DRV_SUP	power_in	Gate driver supply power input; connect 4.7μF ceramic capacitor to PGND, accepts 4V to 12V external supply for FET gate driving or use with REGN for 5V operation.
24	REGN	power_in	Charger internal linear regulator output; 5V LDO output nominally 4.8-5.2V, connect 4.7μF ceramic capacitor to PGND, can supply gate driver circuits up to 70mA.
25	LODRV1	output	Buck-side low-side gate driver output; connect to buck low-side N-channel MOSFET gate.
26	BTST1	power_in	Buck-side high-side gate driver power supply node; connect capacitor between BTST1 and SW1 to provide bias for high-side MOSFET gate driver.
27	HIDRV1	output	Buck-side high-side gate driver output; connect to buck high-side N-channel MOSFET gate.
28	SW1	passive	Buck-side half-bridge switch node; connect inductor between SW1 and SW2 for buck-boost conversion.
29	ACN	input	Adapter current sense resistor negative input; place 0.47μF ceramic capacitor between ACN and ACP for differential filtering and optional 0.1μF to PGND for common-mode filtering.
30	ACP	input	Adapter current sense resistor positive input; place 0.47μF ceramic capacitor between ACN and ACP for differential filtering and 0.1μF ceramic capacitor to PGND for common-mode filtering.
31	ACDRV	output	N-channel input FET gate drive output; drive ACFET gate to 10V when input within ACUV/ACOV window, pull to PGND to turn off FET, connect 15V Zener diode from ACDRV to ACFET source.
32	SYS	input	System voltage detect point; voltage sensing point for system rail, regulated to VSYS_REV in reverse mode when input voltage outside operating window.
33	VAC	power_in	Input voltage detect and power supply node; 4.2V to 70V input bias for IC operation, connect 1μF capacitor between pin and PGND.
34	ACUV	input	Input undervoltage comparator input; connect resistive divider between VAC and PGND to program input undervooltage protection threshold, pull to VAC if unused.
35	ACOV	input	Input overvoltage comparator input; connect resistive divider between VAC and PGND to program input overvoltage protection threshold, pull to PGND if unused.
36	FSW_SYNC	input	Switch frequency and sync input; connect resistor to PGND to program switching frequency from 200kHz to 600kHz, or input external clock from 200kHz to 600kHz for synchronization.
37	Thermal Pad	passive	Exposed thermal pad beneath IC; solder to board and connect via thermal vias to PGND and power ground plane for heat dissipation and thermal performance.

Key specifications

Parameter	Value
Manufacturer	Texas Instruments
Package	VQFN-36-EP(6x5)
Category	Power Management (PMIC)
Pins	37

CAD (KiCad official)

Symbol: BQ25750RRVR
Footprint: Package_DFN_QFN:QFN-36-1EP_5x6mm_P0.5mm_EP3.6x4.6mm
3D model: VQFN-36-EP(6x5) (KiCad packages3D, STEP)
3D model files: bq25750rrvr-etched.step / bq25750rrvr-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); bq25750rrvr.step / bq25750rrvr.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

Datasheet: Texas Instruments datasheet (81 pp, sha256 ea96ae5a890971ff, retrieved 2026-09-23, tier: lcsc)
Datasheet language: Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
Extractor: parts-factory 2.0.0 / extract_pins 0.2, primary claude-haiku-4-5-20251001 (text), consensus claude-sonnet-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF