component
BQ25730RSNR
Public Made by Adomby adom
Texas Instruments Battery Management ICs, QFN-32(4x4). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
3D Model
Open in new tab ↗
Loads when you scroll to it. Unloads after 5 minutes in the background.
Symbol & Footprint
Schematic Symbol
Open full view ↗Loads when you scroll to it. Unloads after 5 minutes in the background.
PCB Footprint
Open full view ↗Loads when you scroll to it. Unloads after 5 minutes in the background.
Datasheet
Open in new tab ↗Loads when you scroll to it. Unloads after 5 minutes in the background.
README
markdownBQ25730RSNR
Texas Instruments · Battery Management ICs · QFN-32(4x4)
BQ25730RSNR from Texas Instruments, in a QFN-32(4x4). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | VBUS | power_in | Charger input voltage; an input low-pass filter of 1 Ω and 0.47 µF (minimum) is recommended. |
| 2 | ACN | input | Input current sense amplifier negative input, leakage matched to ACP, requiring an RC low-pass filter between the sense resistor and the pin. |
| 3 | ACP | input | Input current sense amplifier positive input, leakage matched to ACN, requiring an RC low-pass filter between the sense resistor and the pin. |
| 4 | CHRG_OK | output | Open-drain active-high indicator of a good power source at the input, pulled up via 10 kΩ and high after 50 ms deglitch when VBUS is between 3.5 V and 25.8 V. |
| 5 | OTG/VAP/FRS | input | Active-high input that enables OTG mode (OTG_VAP_MODE=1b and EN_OTG=1b) or FRS mode in forward operation (EN_FRS=1b). |
| 6 | ILIM_HIZ | input | Input current limit setting pin programmed by a resistor divider from VDDA with V(ILIM_HIZ) = 1 V + 40 × IDPM × Rac; below 0.4 V the device enters HIZ mode and above 0.8 V it exits. |
| 7 | VDDA | power_in | Internal reference bias pin; connect a 10-Ω resistor from REGN to VDDA and a 1-µF ceramic capacitor from VDDA to power ground. |
| 8 | IADPT | output | Adapter current monitor output, VIADPT = 20 or 40 × (VACP - VACN), also programs inductance via a resistor to ground (191 kΩ or 187 kΩ for 4.7 µH), clamped below 3.3 V with 100 pF or less decoupling. |
| 9 | IBAT | output | Battery current monitor output, VIBAT = 8 or 16 × (VSRP - VSRN) for charge current, clamped below 3.3 V, with 100 pF or less decoupling and may float if unused. |
| 10 | PSYS | output | Current-mode system power monitor proportional to total adapter and battery power, with a resistor to ground to set the voltage, clamped at 3.3 V and may float if unused. |
| 11 | PROCHOT | output | Active-low open-drain output that pulses when an event in the PROCHOT profile (adapter input current, battery discharge current, system voltage) triggers, with pulse width set by PROCHOT_WIDTH bits. |
| 12 | SDA | bidirectional | I2C open-drain data I/O, connected to the host data line with a 10-kΩ pullup resistor. |
| 13 | SCL | input | I2C clock input from the host controller or smart battery, with a 10-kΩ pullup resistor. |
| 14 | CMPIN | input | Independent comparator input compared with an internal reference, with a resistor to CMPOUT for hysteresis when CMP_POL=1b, and tied to ground if unused. |
| 15 | CMPOUT | output | Open-drain independent comparator output requiring a pullup resistor to the supply rail, floated if the comparator is unused. |
| 16 | COMP1 | passive | Buck-boost converter compensation pin 1 connected to an RC network (see Section 8.3.12). |
| 17 | COMP2 | passive | Buck-boost converter compensation pin 2 connected to an RC network (see Section 8.3.12). |
| 18 | CELL_BATPRESZ | input | Battery cell selection pin for 1- to 5-cell setting biased from VDDA through a resistor divider, which also sets SYSOVP thresholds, indicates battery removal when pulled low, and allows no external capacitor. |
| 19 | SRN | input | Charge current sense amplifier negative input and battery voltage sensing, with a 0.1-µF filter capacitor across the sense resistor and 10-Ω resistor in series, leakage matched to SRP. |
| 20 | SRP | input | Charge current sense amplifier positive input with a 0.1-µF filter capacitor across the sense resistor and 10-Ω resistor in series, leakage matched to SRN. |
| 21 | BATDRV | output | P-channel BATFET gate driver output, shorted to VSYS to turn the BATFET off and driven 10 V below VSYS to turn it fully on. |
| 22 | VSYS | power_in | Charger system voltage sensing, with maximum regulation limit set by ChargeVoltage register plus 150 mV and minimum limit set by the VSYS_MIN register. |
| 23 | SW2 | passive | Boost mode switching node, connected to the source of the boost half-bridge high-side n-channel MOSFET. |
| 24 | HIDRV2 | output | Boost mode high-side power MOSFET (Q4) driver, connected to the high-side n-channel MOSFET gate. |
| 25 | BTST2 | passive | Boost mode high-side MOSFET driver supply; connect a 0.047-µF capacitor between SW2 and BTST2. |
| 26 | LODRV2 | output | Boost mode low-side power MOSFET (Q3) driver, connected to the low-side n-channel MOSFET gate. |
| 27 | PGND | power_in | Device power ground. |
| 28 | REGN | power_out | 6-V linear regulator output from VBUS or VSYS for power stage gate drive, active when VBUS is above VVBUS_CONVEN, with a 2.2- or 3.3-µF ceramic capacitor to power ground. |
| 29 | LODRV1 | output | Buck mode low-side power MOSFET (Q2) driver, connected to the low-side n-channel MOSFET gate. |
| 30 | BTST1 | passive | Buck mode high-side MOSFET driver supply; connect a 0.047-µF capacitor between SW1 and BTST1. |
| 31 | HIDRV1 | output | Buck mode high-side power MOSFET (Q1) driver, connected to the high-side n-channel MOSFET gate. |
| 32 | SW1 | passive | Buck mode switching node, connected to the source of the buck half-bridge high-side n-channel MOSFET. |
| 33 | EP | passive | Exposed pad (from the footprint; not named in the datasheet pin table). |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Texas Instruments |
| Package | QFN-32(4x4) |
| Category | Power Supply Chip |
| Pins | 33 |
Electrical characteristics
Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Input voltage operating range | VINPUT_OP | 3.5 | 26 | V | 9 | ||
| System voltage regulation range | VSYSMAX_RNG | 1.024 | 23.15 | V | measured on VSYS (charge disabled) | 9 | |
| Minimum system voltage regulation range | VSYS_MIN_RNG | 1 | 23 | V | measured on VSYS | 9 | |
| Battery voltage regulation range | VBAT_RNG | 1.024 | 23 | V | 10 | ||
| Battery voltage regulation accuracy 21 V | VBAT_REG_ACC | -0.5 | 0.5 | % | REG0x05/04() = 0x5208H, 0°C to 85°C | 10 | |
| Battery voltage regulation accuracy 4.2 V | VBAT_REG_ACC | -1.1 | 1.45 | % | REG0x05/04() = 0x1068H, 0°C to 85°C | 10 | |
| Charge current regulation accuracy 8192 mA | ICHRG_REG_ACC | -3 | 3 | % | REG0x03/02() = 0x1000H, 5-mΩ RSR, 0°C to 85°C | 10 | |
| Charge current regulation differential voltage range | VIREG_CHG_RNG | 0 | 81.28 | mV | VIREG_CHG = VSRP, VSRN | 10 | |
| Input current regulation accuracy 7800 mA | IIN_DPM_REG_ACC | 7600 | 7800 | 8000 | mA | REG0x0F/0E() = 0x4E00H, 5-mΩ RAC, -40°C to 105°C | 11 |
| Input current regulation accuracy 800 mA | IIN_DPM_REG_ACC | 600 | 800 | 1000 | mA | REG0x0F/0E() = 0x0800H, 5-mΩ RAC, -40°C to 105°C | 11 |
| ACP, ACN leakage current mismatch | ILEAK_ACP_ACN | -16 | 10 | µA | 11 | ||
| ILIM_HIZ leakage current | ILEAK_ILIM | -1 | 1 | µA | 11 | ||
| Input voltage regulation range | VDPM_RNG | 3.2 | 19.52 | V | Voltage on VBUS | 11 | |
| OTG voltage regulation range | VOTG_REG_RNG | 3 | 24 | V | Voltage on VBUS, OOA disabled | 12 | |
| REGN regulator voltage | VREGN_REG | 5.7 | 6 | 6.3 | V | VVBUS = 10 V, 0 mA, 60 mA | 12 |
| REGN voltage in dropout | VDROPOUT | 3.8 | 4.3 | 4.6 | V | VVBUS = 5 V, ILOAD = 20 mA | 12 |
| REGN current limit | IREGN_LIM | 50 | 65 | mA | VVBUS = 10 V, force VREGN = 4 V | 12 | |
| Battery quiescent current, low-power mode | IBAT_BATFET_ON | 22 | 45 | µA | VBAT = 18 V, REG0x01[7] = 1, REG0x31[6] = 0b, low-power mode, Disable PSYS | 12 | |
| Battery quiescent current, performance mode | IBAT_BATFET_ON | 880 | 1170 | µA | VBAT = 18 V, REG0x01[7]= 0, REG0x31[5:4]= 11b, REGN on, Disable PSYS | 12 | |
| ACP/ACN input common mode range | VACP_ACN_OP | 3.8 | 26 | V | Voltage on ACP/ACN | 13 | |
| IADPT output clamp voltage | VIADPT_CLAMP | 3.1 | 3.2 | 3.3 | V | 13 | |
| Input current monitor accuracy | VIADPT_ACC | -2 | 2 | % | V(ACP-ACN) = 40.96 mV | 13 | |
| Battery common mode range | VSRP_SRN_OP | 2.5 | 23.15 | V | Voltage on SRP/SRN | 13 | |
| IBAT output clamp voltage | VIBAT_CLAMP | 3.05 | 3.2 | 3.3 | V | 13 | |
| Charge/discharge current monitor accuracy | IIBAT_CHG_ACC | -2 | 2 | % | V(SRN-SRP) = 40.96 mV | 13 | |
| VSYS undervoltage rising threshold | VSYS_UVLOZ | 2.3 | 2.5 | 2.65 | V | VSYS rising | 14 |
| VSYS undervoltage falling threshold | VSYS_UVLO | 2.2 | 2.4 | 2.55 | V | VSYS falling REG3D[7:5]=000b | 14 |
| VBUS undervoltage rising threshold | VVBUS_UVLOZ | 2.35 | 2.55 | 2.8 | V | VBUS rising | 14 |
| VBUS converter enable rising threshold | VVBUS_CONVEN | 3.2 | 3.5 | 3.9 | V | VBUS rising | 14 |
| VBUS overvoltage rising threshold | VVBUSOV_RISE | 26 | 26.8 | 27.7 | V | VBUS rising | 15 |
| VBUS overvoltage falling threshold | VVBUSOV_FALL | 25 | 25.8 | 26.7 | V | VBUS falling | 15 |
| PWM switching frequency | FSW | 680 | 800 | 920 | kHz | Reg0x01[1] = 0 | 17 |
| PWM switching frequency | FSW | 340 | 400 | 460 | kHz | Reg0x01[1] = 1 | 17 |
| Gate drive voltage on BATFET | VBATDRV_ON | 8.5 | 10 | 11.5 | V | 17 | |
| Thermal shutdown rising temperature | TSHUT_RISE | 155 | °C | Temperature increasing | 16 | ||
| Watchdog timeout period | tWDI | 4 | 5.5 | 7 | s | REG0x01[6:5]=01 | 20 |
| SCL clock frequency | fSCL | 10 | 400 | kHz | 20 | ||
| Voltage SRN, SRP, ACN, ACP, VBUS, VSYS | -0.3 | 32 | V | 8 | |||
| Voltage SW1, SW2 | -2 | 32 | V | 8 | |||
| Voltage BTST1, BTST2, HIDRV1, HIDRV2, BATDRV | -0.3 | 38 | V | 8 | |||
| Junction temperature range | TJ | -40 | 150 | °C | 8 | ||
| Storage temperature | Tstg | -55 | 150 | °C | 8 | ||
| ESD HBM | V(ESD) | -2000 | 2000 | V | HBM, all pins | 8 | |
| ESD CDM | V(ESD) | -500 | 500 | V | CDM, all pins | 8 | |
| Voltage ACN, ACP, VBUS | 0 | 26 | V | 8 | |||
| Voltage SRN, SRP, VSYS | 0 | 23.15 | V | 8 | |||
| Voltage SW1, SW2 | -2 | 26 | V | 8 | |||
| Junction temperature range | TJ | -20 | 125 | °C | 9 | ||
| Storage temperature | Tstg | -20 | 85 | °C | 9 | ||
| Junction-to-ambient thermal resistance | RθJA | 37.2 | °C/W | RSN (WQFN) 32 pins, JEDEC | 9 | ||
| Junction-to-case (top) thermal resistance | RθJC(top) | 26.1 | °C/W | 9 | |||
| Junction-to-board thermal resistance | RθJB | 7.8 | °C/W | 9 | |||
| Junction-to-case (bottom) thermal resistance | RθJC(bot) | 2.3 | °C/W | 9 |
CAD (KiCad official)
- Symbol:
BQ25730RSNR - Footprint:
Package_DFN_QFN:QFN-32-1EP_4x4mm_P0.4mm_EP2.9x2.9mm - 3D model: QFN-32(4x4) (KiCad packages3D, STEP)
- 3D model files:
bq25730rsnr-etched.step/bq25730rsnr-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);bq25730rsnr.step/bq25730rsnr.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: Texas Instruments datasheet (111 pp, sha256
42ecebe67b94f6bf, retrieved 2026-10-22, tier: lcsc) - Datasheet language: Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
- Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-sonnet-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).