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Contents

Pinout
Key specifications
CAD (KiCad official)
Provenance

README

markdown

BQ25713RSNR

Texas Instruments · Battery Management · QFN-32-EP(4x4)

BQ25713RSNR from Texas Instruments, in a QFN-32-EP(4x4). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin	Name	Type	Function
1	VBUS	power_in	Charger input voltage from adapter with 3.5V to 24V operating range.
2	ACN	passive	Input current detection resistor negative input with matched leakage current to ACP pin.
3	ACP	passive	Input current detection resistor positive input with matched leakage current to ACN pin.
4	CHRG_OK	output	Open drain active high indicator output, high when valid input present, low when VBUS <3.2V or >26V with 50ms deglitch.
5	OTG/VAP	input	Active high enable input for OTG or VAP mode operation based on register REG0x34[5] and REG0x35[4] settings.
6	ILIM_HIZ	input	Input current limit setting pin with voltage range 1.15V to 4.0V; enters high impedance mode below 0.4V.
7	VDDA	power_in	Internal reference bias pin requiring 1μF ceramic capacitor to ground for signal conditioning.
8	IADPT	output	Adapter current monitor output with selectable 20V/V or 40V/V gain, clamped to 3.3V maximum output voltage.
9	IBAT	output	Battery current monitor output with selectable 8V/V or 16V/V gain for charge/discharge current, clamped to 3.3V.
10	PSYS	output	System power monitor output current proportional to total input and battery power, gain selectable to 1μA/W or 0.25μA/W.
11	PROCHOT	output	Low active open drain output for processor thermal throttling, monitors adapter current, battery discharge current, and system voltage.
12	SDA	bidirectional	I2C open drain data I/O line requiring 10kΩ pull-up resistor; supports standard and fast mode up to 400kbit/s.
13	SCL	input	I2C clock input requiring 10kΩ pull-up resistor; supports standard and fast mode up to 400kbit/s.
14	CMPIN	input	Independent comparator input with internal 1.2V or 2.3V threshold reference selectable via REG0x30[7].
15	CMPOUT	output	Independent comparator open drain output with programmable deglitch time from 1μs to 5s via REG0x30[5:4].
16	COMP1	passive	Buck/boost converter error amplifier compensation network connection pin 1.
17	COMP2	passive	Buck/boost converter error amplifier compensation network connection pin 2.
18	CELL_BATPRESZ	input	Cell configuration detection pin biased from REGN; determines 1S to 4S battery selection and sets SYSOVP threshold (5V to 19.5V).
19	SRN	passive	Charge current detection resistor negative input also used for battery voltage sensing with matched leakage to SRP.
20	SRP	passive	Charge current detection resistor positive input with matched leakage current to SRN pin for dual-function sensing.
21	BATDRV	output	P-channel battery MOSFET gate driver output with 10V drive voltage when fully on; enables ideal diode in supplement mode.
22	VSYS	power_in	System voltage sensing connection for output regulation with range 1.024V to 19.2V and integrated OVP protection.
23	SW2	passive	Boost mode high-side MOSFET driver source node connection to Q4 source terminal.
24	HIDRV2	output	Boost mode high-side MOSFET (Q4) gate driver output connecting to high-side N-channel MOSFET gate.
25	BTST2	power_in	Boost mode bootstrap supply for high-side gate driver requiring 0.047μF capacitor between SW2 and BTST2.
26	LODRV2	output	Boost mode low-side MOSFET (Q3) gate driver output connecting to low-side N-channel MOSFET gate.
27	PGND	power_in	Device power ground connection to PCB ground plane and thermal pad ground plane via multiple vias.
28	REGN	power_in	6V linear regulator output requiring 2.2μF to 3.3μF ceramic capacitor for stability; powers gate drivers.
29	LODRV1	output	Buck mode low-side MOSFET (Q2) gate driver output connecting to low-side N-channel MOSFET gate.
30	BTST1	power_in	Buck mode bootstrap supply for high-side gate driver requiring 0.047μF capacitor between SW1 and BTST1.
31	HIDRV1	output	Buck mode high-side MOSFET (Q1) gate driver output connecting to high-side N-channel MOSFET gate.
32	SW1	passive	Buck mode high-side MOSFET driver source node connection to Q1 source terminal.
33	EP	passive	Exposed pad (from the footprint; not named in the datasheet pin table).

Key specifications

Parameter	Value
Manufacturer	Texas Instruments
Package	QFN-32-EP(4x4)
Category	Power Management (PMIC)
Pins	33

CAD (KiCad official)

Symbol: BQ25713RSNR
Footprint: Package_DFN_QFN:QFN-32-1EP_4x4mm_P0.4mm_EP2.9x2.9mm
3D model: QFN-32-EP(4x4) (KiCad packages3D, STEP)
3D model files: bq25713rsnr-etched.step / bq25713rsnr-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); bq25713rsnr.step / bq25713rsnr.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

Datasheet: Texas Instruments datasheet (92 pp, sha256 545440f19c8407fe, retrieved 2026-09-24, tier: lcsc)
Datasheet language: Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
Extractor: parts-factory 2.0.0 / extract_pins 0.2, primary claude-haiku-4-5-20251001 (text), consensus claude-sonnet-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF