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BQ25713BRSNR

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Texas Instruments Battery Management, QFN-32-EP(4x4). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

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Contents

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BQ25713BRSNR

Texas Instruments · Battery Management · QFN-32-EP(4x4)

BQ25713BRSNR from Texas Instruments, in a QFN-32-EP(4x4). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 VBUS power_in Charger input voltage, 3.5V to 26V operating range, requires 1Ω and 0.47µF input low-pass filter.
2 ACN input Input current sense resistor negative input, requires RC low-pass filter for high-frequency noise suppression, matched leakage current with ACP.
3 ACP input Input current sense resistor positive input, requires RC low-pass filter for high-frequency noise suppression, matched leakage current with ACN.
4 CHRG_OK output Open-drain active-high indicator for normal power connection, 10kΩ pull-up required, high when VBUS 3.5-24.5V with 50ms debounce.
5 OTG/VAP input Active-high input to enable OTG or VAP mode, controls operation mode based on register REG0x34[5] and REG0x35[4] settings.
6 ILIM_HIZ input Input current limit setting pin, voltage programs limit (V = 1V + 40×IDPM×RAC), enters high-impedance mode below 0.4V.
7 VDDA power_in Internal reference bias pin, requires 10Ω resistor between REGN and VDDA, 1µF ceramic capacitor to ground.
8 IADPT output Adapter current monitor output with gain 20× or 40× of ACP-ACN voltage difference, output clamped at 3.3V, requires ≤100pF capacitor to ground.
9 IBAT output Battery current monitor output with gain 8× or 16× of SRP-SRN voltage difference for charge/discharge, output clamped at 3.3V.
10 PSYS output System power monitor output current proportional to total adapter and battery power, gain selectable via I2C, output clamped at 3.3V.
11 PROCHOT output Processor thermal indicator low-active open-drain output monitoring adapter input current, battery discharge current, and system voltage.
12 SDA bidirectional I2C open-drain data I/O line with 10kΩ pull-up resistor per I2C specification.
13 SCL input I2C clock input with 10kΩ pull-up resistor per I2C specification.
14 CMPIN input Independent comparator input compared to programmable internal reference (1.2V or 2.3V), hysteresis programmable via resistor or fixed 100mV.
15 CMPOUT output Independent comparator open-drain output, requires pull-up resistor, output characteristics and debounce time programmable via I2C.
16 COMP1 input Buck/boost converter compensation pin 1, RC network required for loop compensation.
17 COMP2 input Buck/boost converter compensation pin 2, RC network required for loop compensation.
18 CELL_BATPRESZ input Cell selection pin for 1-4 cell battery configuration, sets SYSOVP thresholds (1S:5V, 2S:12V, 3-4S:19.5V), low pull indicates battery removal.
19 SRN input Charge current sense resistor negative input and battery voltage detection, requires 0.1µF differential capacitor with SRP.
20 SRP input Charge current sense resistor positive input, requires 0.1µF differential capacitor with SRN.
21 BATDRV output P-channel battery FET gate driver output, 10V below VSYS for full conduction, operates in linear mode for system voltage regulation.
22 VSYS input System voltage detection node for regulation, programmable voltage limits in REG0x05/04 and REG0x0D/0C, range 1.024V to 19.2V.
23 SW2 passive Boost mode high-side power MOSFET driver source node, connects to high-side N-channel MOSFET source.
24 HIDRV2 output Boost mode high-side power MOSFET (Q4) driver output, connects to high-side N-channel MOSFET gate.
25 BTST2 power_in Boost mode high-side gate driver power supply, requires 0.047µF bootstrap capacitor between SW2 and BTST2.
26 LODRV2 output Boost mode low-side power MOSFET (Q3) driver output, connects to low-side N-channel MOSFET gate.
27 PGND power_in Device power ground connected to power ground plane.
28 REGN power_out 6V linear regulator output (from VBUS or VSYS), active when VBUS > VVBUS_CONVEN, requires 2.2-3.3µF ceramic capacitor to ground.
29 LODRV1 output Buck mode low-side power MOSFET (Q2) driver output, connects to low-side N-channel MOSFET gate.
30 BTST1 power_in Buck mode high-side gate driver power supply, requires 0.047µF bootstrap capacitor between SW1 and BTST1.
31 HIDRV1 output Buck mode high-side power MOSFET (Q1) driver output, connects to high-side N-channel MOSFET gate.
32 SW1 passive Buck mode high-side power MOSFET driver source node, connects to high-side N-channel MOSFET source.
33 EP passive Exposed pad (from the footprint; not named in the datasheet pin table).

Key specifications

Parameter Value
Manufacturer Texas Instruments
Package QFN-32-EP(4x4)
Category Power Management (PMIC)
Pins 33

CAD (KiCad official)

  • Symbol: BQ25713BRSNR
  • Footprint: Package_DFN_QFN:QFN-32-1EP_4x4mm_P0.4mm_EP2.9x2.9mm
  • 3D model: QFN-32-EP(4x4) (KiCad packages3D, STEP)
  • 3D model files: bq25713brsnr-etched.step / bq25713brsnr-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); bq25713brsnr.step / bq25713brsnr.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Texas Instruments datasheet (92 pp, sha256 545440f19c8407fe, retrieved 2026-10-05, tier: lcsc)
  • Datasheet language: Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-4-5-20251001 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF