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BQ25616JRTWT

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Texas Instruments Battery Management, WQFN-24(4x4). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

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BQ25616JRTWT

Texas Instruments · Battery Management · WQFN-24(4x4)

BQ25616JRTWT from Texas Instruments, in a WQFN-24(4x4). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 VAC power_in Charger input voltage sensing; an optional external n-channel ACFET is placed between VAC and VBUS, and VAC is connected to VBUS if the ACFET is not used. The ACFET turns on when VAC is below the 14.2 V ACOV threshold and above UVLO.
2 ACDRV output Charge pump output that drives an external N-channel ACFET, providing 6 V above VBUS as gate drive; leave floating if external OVP is not used.
3 D+ bidirectional Positive line of the USB data pair used for D+/D- based host/charging port detection (DCD, BC1.2 primary and secondary detection, and nonstandard adapters).
4 D- bidirectional Negative line of the USB data pair used for D+/D- based host/charging port detection (DCD, BC1.2 primary and secondary detection, and nonstandard adapters).
5 STAT output Open-drain status output that must be pulled up to a logic rail through 10 kΩ; LOW indicates charge in progress, HIGH indicates charge complete or SLEEP, and 1 Hz blinking indicates charge suspend (fault). Sink current is limited to 6 mA.
6 OTG input Boost mode enable pin; boost mode is enabled when pulled HIGH, and the pin must not be left floating.
7 PG output Open-drain active-low power-good output, pulled up through 10 kΩ; LOW indicates a good input when VIN is between UVLO and ACOV, above the SLEEP threshold, and input current limit is above 30 mA. Sink current is limited to 6 mA.
8 ILIM input Sets the input current limit via a resistor to ground (IINDPM = KILIM/RILIM) when the adapter is detected as unknown; acceptable range is 500 mA to 3200 mA.
9 CE input Charge enable pin; battery charging is enabled when this pin is driven LOW.
10 ICHG input Sets the charge current limit via a resistor to ground (ICHG = KICHG/RICHG); acceptable charge current range is 300 mA to 3000 mA.
11 TS input Battery temperature qualification input for an NTC thermistor, with a resistor divider from REGN to TS to GND; charge and boost are suspended when the TS voltage is out of range (10 kΩ resistors to REGN and GND when unused).
12 VSET input Sets the default battery charge voltage via a resistor to GND: float = 4.208 V, short to GND = 4.352 V, 5 kΩ to 25 kΩ = 4.100 V.
13 BAT power_in Battery connection to the positive terminal of the battery pack; the internal current sense resistor is between SYS and BAT, and a 10 µF capacitor should be placed close to this pin.
14 BAT power_in Battery connection to the positive terminal of the battery pack; the internal current sense resistor is between SYS and BAT, and a 10 µF capacitor should be placed close to this pin.
15 SYS power_out System output connection point; the internal current sense resistor is between SYS and BAT, and a 10 µF (min) capacitor should be placed close to this pin.
16 SYS power_out System output connection point; the internal current sense resistor is between SYS and BAT, and a 10 µF (min) capacitor should be placed close to this pin.
17 GND power_in Power ground and signal ground.
18 GND power_in Power ground and signal ground.
19 SW power_out Switching node connecting to the output inductor, internally tied to the HSFET source and LSFET drain; connect the 0.047 µF bootstrap capacitor from SW to BTST.
20 SW power_out Switching node connecting to the output inductor, internally tied to the HSFET source and LSFET drain; connect the 0.047 µF bootstrap capacitor from SW to BTST.
21 BTST power_in PWM high-side driver positive supply, connected internally to the bootstrap diode cathode; connect the 0.047 µF bootstrap capacitor from SW to BTST.
22 REGN power_out PWM low-side driver positive supply output, connected to the bootstrap diode anode; connect a 4.7 µF (10 V rated) ceramic capacitor from REGN to analog GND close to the IC.
23 PMID power_out Connected to the drain of the reverse blocking MOSFET (RBFET) and the drain of HSFET; place a 10 µF capacitor from PMID to GND.
24 VBUS power_in Charger input voltage; the internal RBFET is between VBUS (source) and PMID, and a 1 µF ceramic capacitor should be placed from VBUS to GND as close as possible to the device.
25 PAD passive Exposed pad (from the footprint; not named in the datasheet pin table).

Key specifications

Parameter Value
Manufacturer Texas Instruments
Package WQFN-24(4x4)
Category Power Management (PMIC)
Pins 25

CAD (KiCad official)

  • Symbol: BQ25616JRTWT
  • Footprint: Package_DFN_QFN:QFN-24-1EP_4x4mm_P0.5mm_EP2.7x2.7mm
  • 3D model: WQFN-24(4x4) (KiCad packages3D, STEP)
  • 3D model files: bq25616jrtwt-etched.step / bq25616jrtwt-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); bq25616jrtwt.step / bq25616jrtwt.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Texas Instruments datasheet (50 pp, sha256 7be49ad55a7694f6, retrieved 2026-10-08, tier: lcsc)
  • Datasheet language: Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF