BQ25611DRTWR

Texas Instruments · Battery Management · WQFN-24(4x4)

BQ25611DRTWR from Texas Instruments, in a WQFN-24(4x4). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin	Name	Type	Function
1	VAC	power_in	Input voltage sensing pin that must be tied to VBUS.
2	D+	bidirectional	Positive line of the USB data pair used for D+/D- based host/charging port detection, including data contact detection and BC1.2 primary and secondary detection and nonstandard adapters.
3	D-	bidirectional	Negative line of the USB data pair used for D+/D- based host/charging port detection, including data contact detection and BC1.2 primary and secondary detection and nonstandard adapters.
4	STAT	output	Open-drain charger status output that is LOW during charge in progress, HIGH on charge complete or SLEEP mode, and blinks at 1 Hz on charge suspend fault; connect to a logic rail through 10 kΩ.
5	SCL	input	I2C interface clock input that must be connected to the logic rail through a 10 kΩ resistor.
6	SDA	bidirectional	I2C interface data line that must be connected to the logic rail through a 10 kΩ resistor.
7	INT	output	Open-drain interrupt output that sends an active-low 256 µs pulse to the host to report charger status and faults; connect to a logic rail through a 10 kΩ resistor.
8	NC	unconnected	Not connected.
9	CE	input	Charge enable input; battery charging is enabled when this pin is driven LOW.
10	BATSNS	input	Battery voltage sensing input for charge voltage regulation, connected to the battery positive terminal; if open or shorted to ground, BATSNS_STAT is set to 1 and the charger regulates the battery voltage through the BAT pin.
11	TS	input	Battery temperature qualification input for an NTC thermistor; charge and boost mode are suspended when the TS voltage is out of range, and it should be tied to REGN and GND with 10 kΩ resistors or TS_IGNORE set HIGH when unused.
12	QON	input	BATFET enable/reset control input with a 200 kΩ pull-up to VQON and an internal 6.5 V clamp; a LOW of tSHIPMODE exits ship mode, and a LOW of tQON_RST (minimum 8 s) resets the system by turning off the BATFET for tBATFET_RST (minimum 250 ms).
13	BAT	power_in	Battery connection to the positive terminal of the battery pack; the internal current sensing resistor is between SYS and BAT, and a 10 µF capacitor should be placed close to this pin.
14	BAT	power_in	Battery connection to the positive terminal of the battery pack; the internal current sensing resistor is between SYS and BAT, and a 10 µF capacitor should be placed close to this pin.
15	SYS	power_out	System output connection point; the internal current sensing resistor is between SYS and BAT, and a 10 µF (minimum) capacitor should be placed close to this pin.
16	SYS	power_out	System output connection point; the internal current sensing resistor is between SYS and BAT, and a 10 µF (minimum) capacitor should be placed close to this pin.
17	GND	power_in	Ground reference for the device.
18	GND	power_in	Ground reference for the device.
19	SW	passive	Switching node connected to the output inductor and internally to the HSFET source and LSFET drain; a 0.047 µF bootstrap capacitor connects from SW to BTST.
20	SW	passive	Switching node connected to the output inductor and internally to the HSFET source and LSFET drain; a 0.047 µF bootstrap capacitor connects from SW to BTST.
21	BTST	passive	PWM high-side driver positive supply connected internally to the bootstrap diode cathode; connect a 0.047 µF bootstrap capacitor from SW to BTST.
22	REGN	power_out	PWM low-side driver positive supply output connected to the bootstrap diode anode; connect a 4.7 µF (10 V rating) ceramic capacitor from REGN to analog GND close to the IC.
23	PMID	passive	Connected to the drain of the reverse blocking MOSFET (RBFET) and the drain of HSFET; place a 10 µF capacitor from PMID to GND.
24	VBUS	power_in	Charger input voltage with an internal RBFET between VBUS and PMID; place a 1 µF ceramic capacitor from VBUS to GND as close as possible to the device, and the absolute maximum input rating is 22 V.
25	Thermal Pad	passive	Exposed pad (from the footprint; not named in the datasheet pin table).

Key specifications

Parameter	Value
Manufacturer	Texas Instruments
Package	WQFN-24(4x4)
Category	Power Management (PMIC)
Pins	25

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter	Symbol	Min	Typ	Max	Unit	Conditions	Page
Voltage VAC (converter not switching)	VAC	-2		22	V	converter not switching	6
Voltage VBUS (converter not switching)	VBUS	-2		22	V	converter not switching	6
Voltage PMID (converter not switching)	PMID	-0.3		22	V	converter not switching	6
Voltage SW	SW	-0.3		16	V		6
Voltage BAT, SYS (converter not switching)	BAT, SYS	-0.3		7	V	converter not switching	6
Voltage BTST	BTST	-0.3		22	V		6
Voltage BATSNS (converter not switching)	BATSNS	-0.3		7	V	converter not switching	6
Voltage D+, D-, STAT, SCL, SDA, INT, CE, TS, QON, REGN	D+, D-, STAT, SCL, SDA, INT, CE, TS, QON, REGN	-0.3		7	V		6
Output sink current STAT, INT				6	mA		6
TJ Junction temperature	TJ	-40		150	°C		6
Tstg Storage temperature	Tstg	-55		150	°C		6
Input voltage	VVBUS	4		13.5	V		6
Ambient temperature	TA	-40		85	°C		6
Junction-to-ambient thermal resistance (JEDEC)	RθJA		35.6		°C/W	RTW (WQFN) 24 pins	6
Junction-to-case (top) thermal resistance	RθJC(top)		22.7		°C/W	RTW (WQFN) 24 pins	6
Junction-to-board thermal resistance	RθJB		11.9		°C/W	RTW (WQFN) 24 pins	7
Junction-to-top characterization parameter	ΨJT		0.2		°C/W	RTW (WQFN) 24 pins	7
Junction-to-board characterization parameter	ΨJB		1.2		°C/W	RTW (WQFN) 24 pins	7
Junction-to-case (bottom) thermal resistance	RθJC(bot)		2.6		°C/W	RTW (WQFN) 24 pins	7
Quiescent battery current (BATSNS, BAT, SYS, SW)	IQ_BAT		9.5	15	µA	VBAT = 4.5 V, VBUS floating or 0-5 V, SCL/SDA = 0 V or 1.8 V, TJ < 85°C, BATFET enabled	7
Shipmode battery current (BATSNS, BAT, SYS, SW)	ISHIP_BAT		7	9.5	µA	VBAT = 4.5 V, VBUS floating or 0-5 V, SCL/SDA = 0 V or 1.8 V, TJ < 85°C, BATFET disabled	7
Quiescent input current in HIZ (5 V)	IHIZ_VBUS		37	50	µA	VAC/VBUS = 5 V, HIZ mode, no battery	7
Quiescent input current in HIZ (12 V)	IHIZ_VBUS		68	90	µA	VAC/VBUS = 12 V, HIZ mode, no battery	7
VBUS operating range	VVBUS_OP	4		13.5	V		7
VBUS rising for active I2C, no battery	VVBUS_UVLOZ	3.3		3.7	V	VBUS rising	7
VBUS falling to turnoff I2C, no battery	VVBUS_UVLO	3		3.3	V	VBUS falling	7
VBUS to enable REGN	VVBUS_PRESENT	3.65		3.9	V	VBUS rising	7
VBUS to disable REGN	VVBUS_PRESENTZ	3.15		3.4	V	VBUS falling	7
Enter Sleep mode threshold (VBUS - VBAT)	VSLEEP	15	60	110	mV	VBUS falling, VBAT = 4 V	7
Exit Sleep mode threshold (VBUS - VBAT)	VSLEEPZ	115	220	340	mV	VBUS rising, VBAT = 4 V	7
VAC overvoltage rising threshold to turn off switching (default)	VACOV	13.5	14.2	14.85	V	VAC rising, OVP[1:0]=11 (default)	7
VAC overvoltage falling threshold to resume switching (default)	VACOV	13	13.9	14.5	V	VAC falling, OVP[1:0]=11 (default)	7
BAT depletion falling threshold to turn off BATFET	VBAT_DPL	2.18	2.4	2.55	V	VBAT falling	8
Bad adapter detection threshold	VPOORSRC	3.75	3.9	4	V	VBUS falling	8
Typical charge voltage regulation range	VREG_RANGE	3.49		4.51	V		8
Charge voltage accuracy (4.09 V)	VREG_ACC	4.073	4.09	4.106	V	VREG = 4.09 V, TJ = -40°C to 85°C	8
Charge voltage accuracy (4.19 V)	VREG_ACC	4.173	4.19	4.2	V	VREG = 4.19 V, TJ = -40°C to 85°C	8
Charge voltage accuracy (4.35 V)	VREG_ACC	4.332	4.35	4.367	V	VREG = 4.35 V, TJ = -40°C to 85°C	8
Charge voltage accuracy (4.45 V)	VREG_ACC	4.432	4.45	4.468	V	VREG = 4.45 V, TJ = -40°C to 85°C	8
Fast charge current regulation accuracy (0.24 A)	ICHG_ACC	0.2112	0.24	0.2688	A	ICHG = 0.24 A, VBAT = 3.1 V or 3.8 V, TJ = -40°C to 85°C	8
Fast charge current regulation accuracy (0.72 A)	ICHG_ACC	0.6768	0.72	0.7632	A	ICHG = 0.72 A, VBAT = 3.1 V or 3.8 V, TJ = -40°C to 85°C	8
Fast charge current regulation accuracy (1.38 A)	ICHG_ACC	1.2972	1.38	1.4628	A	ICHG = 1.38 A, VBAT = 3.1 V or 3.8 V, TJ = -40°C to 85°C	8
Precharge current accuracy (120 mA)	IPRECHG_ACC	102	120	138	mA	VBAT = 2.6 V, IPRECHG = 120 mA	8
Precharge current accuracy (240 mA)	IPRECHG_ACC	204	240	276	mA	VBAT = 2.6 V, IPRECHG = 240 mA	8
Termination current accuracy (180 mA)	ITERM_ACC	162	180	192	mA	ITERM = 180 mA, ICHG > 780 mA, VREG = 4.35 V, TJ = -40°C to 85°C	8
Termination current accuracy (60 mA)	ITERM_ACC	42	60	78	mA	ITERM = 60 mA, ICHG < 780 mA, VREG = 4.35 V, TJ = -40°C to 85°C	8
Battery FET on-resistance	RON_BATFET		19.5	26	mΩ	TJ = -40°C to 85°C	9
Battery overvoltage rising threshold	VBAT_OVP	103	104	105	%	VBAT rising, as percentage of VREG	9
Battery overvoltage falling threshold	VBAT_OVP	101	102	103	%	VBAT falling, as percentage of VREG	9
Input voltage regulation accuracy	VINDPM_ACC	4.365	4.5	4.635	V		9
Input current regulation accuracy (500 mA)	IINDPM_ACC	450	465	500	mA	IINDPM = 500 mA, TJ = -40°C to 85°C	9
Input current regulation accuracy (1500 mA)	IINDPM_ACC	1300	1390	1500	mA	IINDPM = 1500 mA, TJ = -40°C to 85°C	9
D+ line source voltage	VDP_SRC	500	600	700	mV		9
D- line source voltage	VDM_SRC	500	600	700	mV		9
TS pin voltage rising threshold (charge suspended)	VT1_RISE%	72.4	73.3	74.2	%	As percentage to REGN (0°C w/ 103AT)	10
PWM switching frequency	FSW	1.32	1.5	1.68	MHz	Oscillator frequency	11
Boost mode voltage regulation accuracy	VBST_ACC	4.85	5	5.15	V	IVBUS = 0 A, BOOST_V = 5 V	11
Boost mode maximum output current limit	IBST_ACC	1.2	1.4	1.6	A		11
REGN LDO output voltage (5 V input)	VREGN	4.58	4.7	4.8	V	VVBUS = 5 V, IREGN = 20 mA	11
HSFET cycle-by-cycle overcurrent threshold	IHSFET_OCP	5.2		8	A		12

Materials and finish

As the datasheet states them (page.json metadata.appearance; the 3D model's colours follow it).

Part	Material	Colour / plating	Datasheet says	Page
contacts	copper		1. Place input capacitor as close as possible to PMID pin and GND pin connections and use shortest copper	51

CAD (KiCad official)

Symbol: BQ25611DRTWR
Footprint: Package_DFN_QFN:QFN-24-1EP_4x4mm_P0.5mm_EP2.6x2.6mm
3D model: WQFN-24(4x4) (KiCad packages3D, STEP)
3D model files: bq25611drtwr-etched.step / bq25611drtwr-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); bq25611drtwr.step / bq25611drtwr.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

Datasheet: Texas Instruments datasheet (63 pp, sha256 389b6ef272ca0182, retrieved 2026-10-20, tier: lcsc)
Datasheet language: Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF

# BQ25611DRTWR

**Texas Instruments** · Battery Management · WQFN-24(4x4)

BQ25611DRTWR from Texas Instruments, in a WQFN-24(4x4). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

## Pinout

| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | VAC | power_in | Input voltage sensing pin that must be tied to VBUS. |
| 2 | D+ | bidirectional | Positive line of the USB data pair used for D+/D- based host/charging port detection, including data contact detection and BC1.2 primary and secondary detection and nonstandard adapters. |
| 3 | D- | bidirectional | Negative line of the USB data pair used for D+/D- based host/charging port detection, including data contact detection and BC1.2 primary and secondary detection and nonstandard adapters. |
| 4 | STAT | output | Open-drain charger status output that is LOW during charge in progress, HIGH on charge complete or SLEEP mode, and blinks at 1 Hz on charge suspend fault; connect to a logic rail through 10 kΩ. |
| 5 | SCL | input | I2C interface clock input that must be connected to the logic rail through a 10 kΩ resistor. |
| 6 | SDA | bidirectional | I2C interface data line that must be connected to the logic rail through a 10 kΩ resistor. |
| 7 | INT | output | Open-drain interrupt output that sends an active-low 256 µs pulse to the host to report charger status and faults; connect to a logic rail through a 10 kΩ resistor. |
| 8 | NC | unconnected | Not connected. |
| 9 | CE | input | Charge enable input; battery charging is enabled when this pin is driven LOW. |
| 10 | BATSNS | input | Battery voltage sensing input for charge voltage regulation, connected to the battery positive terminal; if open or shorted to ground, BATSNS_STAT is set to 1 and the charger regulates the battery voltage through the BAT pin. |
| 11 | TS | input | Battery temperature qualification input for an NTC thermistor; charge and boost mode are suspended when the TS voltage is out of range, and it should be tied to REGN and GND with 10 kΩ resistors or TS_IGNORE set HIGH when unused. |
| 12 | QON | input | BATFET enable/reset control input with a 200 kΩ pull-up to VQON and an internal 6.5 V clamp; a LOW of tSHIPMODE exits ship mode, and a LOW of tQON_RST (minimum 8 s) resets the system by turning off the BATFET for tBATFET_RST (minimum 250 ms). |
| 13 | BAT | power_in | Battery connection to the positive terminal of the battery pack; the internal current sensing resistor is between SYS and BAT, and a 10 µF capacitor should be placed close to this pin. |
| 14 | BAT | power_in | Battery connection to the positive terminal of the battery pack; the internal current sensing resistor is between SYS and BAT, and a 10 µF capacitor should be placed close to this pin. |
| 15 | SYS | power_out | System output connection point; the internal current sensing resistor is between SYS and BAT, and a 10 µF (minimum) capacitor should be placed close to this pin. |
| 16 | SYS | power_out | System output connection point; the internal current sensing resistor is between SYS and BAT, and a 10 µF (minimum) capacitor should be placed close to this pin. |
| 17 | GND | power_in | Ground reference for the device. |
| 18 | GND | power_in | Ground reference for the device. |
| 19 | SW | passive | Switching node connected to the output inductor and internally to the HSFET source and LSFET drain; a 0.047 µF bootstrap capacitor connects from SW to BTST. |
| 20 | SW | passive | Switching node connected to the output inductor and internally to the HSFET source and LSFET drain; a 0.047 µF bootstrap capacitor connects from SW to BTST. |
| 21 | BTST | passive | PWM high-side driver positive supply connected internally to the bootstrap diode cathode; connect a 0.047 µF bootstrap capacitor from SW to BTST. |
| 22 | REGN | power_out | PWM low-side driver positive supply output connected to the bootstrap diode anode; connect a 4.7 µF (10 V rating) ceramic capacitor from REGN to analog GND close to the IC. |
| 23 | PMID | passive | Connected to the drain of the reverse blocking MOSFET (RBFET) and the drain of HSFET; place a 10 µF capacitor from PMID to GND. |
| 24 | VBUS | power_in | Charger input voltage with an internal RBFET between VBUS and PMID; place a 1 µF ceramic capacitor from VBUS to GND as close as possible to the device, and the absolute maximum input rating is 22 V. |
| 25 | Thermal Pad | passive | Exposed pad (from the footprint; not named in the datasheet pin table). |

## Key specifications

| Parameter | Value |
|---|---|
| Manufacturer | Texas Instruments |
| Package | WQFN-24(4x4) |
| Category | Power Management (PMIC) |
| Pins | 25 |

## Electrical characteristics

Limits as printed in the datasheet (page.json `metadata.characteristics` carries them as data).

| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Voltage VAC (converter not switching) | VAC | -2 |  | 22 | V | converter not switching | 6 |
| Voltage VBUS (converter not switching) | VBUS | -2 |  | 22 | V | converter not switching | 6 |
| Voltage PMID (converter not switching) | PMID | -0.3 |  | 22 | V | converter not switching | 6 |
| Voltage SW | SW | -0.3 |  | 16 | V |  | 6 |
| Voltage BAT, SYS (converter not switching) | BAT, SYS | -0.3 |  | 7 | V | converter not switching | 6 |
| Voltage BTST | BTST | -0.3 |  | 22 | V |  | 6 |
| Voltage BATSNS (converter not switching) | BATSNS | -0.3 |  | 7 | V | converter not switching | 6 |
| Voltage D+, D-, STAT, SCL, SDA, INT, CE, TS, QON, REGN | D+, D-, STAT, SCL, SDA, INT, CE, TS, QON, REGN | -0.3 |  | 7 | V |  | 6 |
| Output sink current STAT, INT |  |  |  | 6 | mA |  | 6 |
| TJ Junction temperature | TJ | -40 |  | 150 | °C |  | 6 |
| Tstg Storage temperature | Tstg | -55 |  | 150 | °C |  | 6 |
| Input voltage | VVBUS | 4 |  | 13.5 | V |  | 6 |
| Ambient temperature | TA | -40 |  | 85 | °C |  | 6 |
| Junction-to-ambient thermal resistance (JEDEC) | RθJA |  | 35.6 |  | °C/W | RTW (WQFN) 24 pins | 6 |
| Junction-to-case (top) thermal resistance | RθJC(top) |  | 22.7 |  | °C/W | RTW (WQFN) 24 pins | 6 |
| Junction-to-board thermal resistance | RθJB |  | 11.9 |  | °C/W | RTW (WQFN) 24 pins | 7 |
| Junction-to-top characterization parameter | ΨJT |  | 0.2 |  | °C/W | RTW (WQFN) 24 pins | 7 |
| Junction-to-board characterization parameter | ΨJB |  | 1.2 |  | °C/W | RTW (WQFN) 24 pins | 7 |
| Junction-to-case (bottom) thermal resistance | RθJC(bot) |  | 2.6 |  | °C/W | RTW (WQFN) 24 pins | 7 |
| Quiescent battery current (BATSNS, BAT, SYS, SW) | IQ_BAT |  | 9.5 | 15 | µA | VBAT = 4.5 V, VBUS floating or 0-5 V, SCL/SDA = 0 V or 1.8 V, TJ < 85°C, BATFET enabled | 7 |
| Shipmode battery current (BATSNS, BAT, SYS, SW) | ISHIP_BAT |  | 7 | 9.5 | µA | VBAT = 4.5 V, VBUS floating or 0-5 V, SCL/SDA = 0 V or 1.8 V, TJ < 85°C, BATFET disabled | 7 |
| Quiescent input current in HIZ (5 V) | IHIZ_VBUS |  | 37 | 50 | µA | VAC/VBUS = 5 V, HIZ mode, no battery | 7 |
| Quiescent input current in HIZ (12 V) | IHIZ_VBUS |  | 68 | 90 | µA | VAC/VBUS = 12 V, HIZ mode, no battery | 7 |
| VBUS operating range | VVBUS_OP | 4 |  | 13.5 | V |  | 7 |
| VBUS rising for active I2C, no battery | VVBUS_UVLOZ | 3.3 |  | 3.7 | V | VBUS rising | 7 |
| VBUS falling to turnoff I2C, no battery | VVBUS_UVLO | 3 |  | 3.3 | V | VBUS falling | 7 |
| VBUS to enable REGN | VVBUS_PRESENT | 3.65 |  | 3.9 | V | VBUS rising | 7 |
| VBUS to disable REGN | VVBUS_PRESENTZ | 3.15 |  | 3.4 | V | VBUS falling | 7 |
| Enter Sleep mode threshold (VBUS - VBAT) | VSLEEP | 15 | 60 | 110 | mV | VBUS falling, VBAT = 4 V | 7 |
| Exit Sleep mode threshold (VBUS - VBAT) | VSLEEPZ | 115 | 220 | 340 | mV | VBUS rising, VBAT = 4 V | 7 |
| VAC overvoltage rising threshold to turn off switching (default) | VACOV | 13.5 | 14.2 | 14.85 | V | VAC rising, OVP[1:0]=11 (default) | 7 |
| VAC overvoltage falling threshold to resume switching (default) | VACOV | 13 | 13.9 | 14.5 | V | VAC falling, OVP[1:0]=11 (default) | 7 |
| BAT depletion falling threshold to turn off BATFET | VBAT_DPL | 2.18 | 2.4 | 2.55 | V | VBAT falling | 8 |
| Bad adapter detection threshold | VPOORSRC | 3.75 | 3.9 | 4 | V | VBUS falling | 8 |
| Typical charge voltage regulation range | VREG_RANGE | 3.49 |  | 4.51 | V |  | 8 |
| Charge voltage accuracy (4.09 V) | VREG_ACC | 4.073 | 4.09 | 4.106 | V | VREG = 4.09 V, TJ = -40°C to 85°C | 8 |
| Charge voltage accuracy (4.19 V) | VREG_ACC | 4.173 | 4.19 | 4.2 | V | VREG = 4.19 V, TJ = -40°C to 85°C | 8 |
| Charge voltage accuracy (4.35 V) | VREG_ACC | 4.332 | 4.35 | 4.367 | V | VREG = 4.35 V, TJ = -40°C to 85°C | 8 |
| Charge voltage accuracy (4.45 V) | VREG_ACC | 4.432 | 4.45 | 4.468 | V | VREG = 4.45 V, TJ = -40°C to 85°C | 8 |
| Fast charge current regulation accuracy (0.24 A) | ICHG_ACC | 0.2112 | 0.24 | 0.2688 | A | ICHG = 0.24 A, VBAT = 3.1 V or 3.8 V, TJ = -40°C to 85°C | 8 |
| Fast charge current regulation accuracy (0.72 A) | ICHG_ACC | 0.6768 | 0.72 | 0.7632 | A | ICHG = 0.72 A, VBAT = 3.1 V or 3.8 V, TJ = -40°C to 85°C | 8 |
| Fast charge current regulation accuracy (1.38 A) | ICHG_ACC | 1.2972 | 1.38 | 1.4628 | A | ICHG = 1.38 A, VBAT = 3.1 V or 3.8 V, TJ = -40°C to 85°C | 8 |
| Precharge current accuracy (120 mA) | IPRECHG_ACC | 102 | 120 | 138 | mA | VBAT = 2.6 V, IPRECHG = 120 mA | 8 |
| Precharge current accuracy (240 mA) | IPRECHG_ACC | 204 | 240 | 276 | mA | VBAT = 2.6 V, IPRECHG = 240 mA | 8 |
| Termination current accuracy (180 mA) | ITERM_ACC | 162 | 180 | 192 | mA | ITERM = 180 mA, ICHG > 780 mA, VREG = 4.35 V, TJ = -40°C to 85°C | 8 |
| Termination current accuracy (60 mA) | ITERM_ACC | 42 | 60 | 78 | mA | ITERM = 60 mA, ICHG < 780 mA, VREG = 4.35 V, TJ = -40°C to 85°C | 8 |
| Battery FET on-resistance | RON_BATFET |  | 19.5 | 26 | mΩ | TJ = -40°C to 85°C | 9 |
| Battery overvoltage rising threshold | VBAT_OVP | 103 | 104 | 105 | % | VBAT rising, as percentage of VREG | 9 |
| Battery overvoltage falling threshold | VBAT_OVP | 101 | 102 | 103 | % | VBAT falling, as percentage of VREG | 9 |
| Input voltage regulation accuracy | VINDPM_ACC | 4.365 | 4.5 | 4.635 | V |  | 9 |
| Input current regulation accuracy (500 mA) | IINDPM_ACC | 450 | 465 | 500 | mA | IINDPM = 500 mA, TJ = -40°C to 85°C | 9 |
| Input current regulation accuracy (1500 mA) | IINDPM_ACC | 1300 | 1390 | 1500 | mA | IINDPM = 1500 mA, TJ = -40°C to 85°C | 9 |
| D+ line source voltage | VDP_SRC | 500 | 600 | 700 | mV |  | 9 |
| D- line source voltage | VDM_SRC | 500 | 600 | 700 | mV |  | 9 |
| TS pin voltage rising threshold (charge suspended) | VT1_RISE% | 72.4 | 73.3 | 74.2 | % | As percentage to REGN (0°C w/ 103AT) | 10 |
| PWM switching frequency | FSW | 1.32 | 1.5 | 1.68 | MHz | Oscillator frequency | 11 |
| Boost mode voltage regulation accuracy | VBST_ACC | 4.85 | 5 | 5.15 | V | IVBUS = 0 A, BOOST_V = 5 V | 11 |
| Boost mode maximum output current limit | IBST_ACC | 1.2 | 1.4 | 1.6 | A |  | 11 |
| REGN LDO output voltage (5 V input) | VREGN | 4.58 | 4.7 | 4.8 | V | VVBUS = 5 V, IREGN = 20 mA | 11 |
| HSFET cycle-by-cycle overcurrent threshold | IHSFET_OCP | 5.2 |  | 8 | A |  | 12 |

## Materials and finish

As the datasheet states them (page.json `metadata.appearance`; the 3D model's colours follow it).

| Part | Material | Colour / plating | Datasheet says | Page |
|---|---|---|---|---|
| contacts | copper |  | 1. Place input capacitor as close as possible to PMID pin and GND pin connections and use shortest copper | 51 |

## CAD (KiCad official)

- Symbol: `BQ25611DRTWR`
- Footprint: `Package_DFN_QFN:QFN-24-1EP_4x4mm_P0.5mm_EP2.6x2.6mm`
- 3D model: WQFN-24(4x4) (KiCad packages3D, STEP)
- 3D model files: `bq25611drtwr-etched.step` / `bq25611drtwr-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `bq25611drtwr.step` / `bq25611drtwr.glb` are the bare package body.

## Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

- **Datasheet:** [Texas Instruments datasheet](https://www.ti.com/cn/lit/gpn/bq25611d) (63 pp, sha256 `389b6ef272ca0182`, retrieved 2026-10-20, tier: lcsc)
- **Datasheet language:** Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.3`, primary `claude-haiku-5-5` (text), consensus `claude-sonnet-5-5` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
- **CAD:** KiCad official libraries (CC-BY-SA 4.0).

[Datasheet PDF](docs/bq25611drtwr-datasheet.pdf)