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BQ25601DRTWR
Public Made by Adomby adom
Texas Instruments Battery Management ICs, WQFN-24-EP(4x4). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
3D Model
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Symbol & Footprint
Schematic Symbol
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PCB Footprint
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Datasheet
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Contents
README
markdownBQ25601DRTWR
Texas Instruments · Battery Management ICs · WQFN-24-EP(4x4)
BQ25601DRTWR from Texas Instruments, in a WQFN-24-EP(4x4). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | VBUS | power_in | Charger input; the internal n-channel reverse blocking MOSFET (RBFET) is connected between VBUS and PMID, with a 1-uF ceramic capacitor placed from VBUS to GND close to the device. |
| 2 | D+ | bidirectional | Positive line of the USB data pair used for D+/D- based USB host/charging port detection, including data contact detection, BC1.2 primary and secondary detection and nonstandard adaptors. |
| 3 | D- | bidirectional | Negative line of the USB data pair used for D+/D- based USB host/charging port detection, including data contact detection, BC1.2 primary and secondary detection and nonstandard adaptors. |
| 4 | STAT | output | Open-drain charge status output (low while charging, high when charge complete or in sleep, 1-Hz pulses on charge suspend), connected to a logic rail via 10 kΩ and disabled via EN_ICHG_MON[1:0] bits. |
| 5 | SCL | input | I2C interface clock; connect to the logic rail through a 10-kΩ resistor. |
| 6 | SDA | bidirectional | I2C interface data; connect to the logic rail through a 10-kΩ resistor. |
| 7 | INT | output | Open-drain interrupt output that sends an active-low 256-µs pulse to the host to report charger status and faults, connected to a logic rail through a 10-kΩ resistor. |
| 8 | NC | unconnected | No connect; keep the pin floating. |
| 9 | CE | input | Charge enable pin; battery charging is enabled when this pin is driven low. |
| 10 | NC | unconnected | No connect; keep the pin floating. |
| 11 | TS | input | Temperature qualification voltage input supporting the JEITA profile with an NTC thermistor (103AT-2 recommended); charge suspends when out of range, and if unused connect 10 kΩ from REGN to TS and 10 kΩ from TS to GND. |
| 12 | QON | input | BATFET enable/reset control input with internal pull-up; a low of tSHIPMODE exits ship mode, and a low of tQON_RST (minimum 8 s) with VBUS absent resets SYS by turning BATFET off for at least 250 ms. |
| 13 | BAT | bidirectional | Battery connection point to the positive terminal of the battery pack, with the internal BATFET and current sensing between SYS and BAT; connect 10 µF close to the pin. |
| 14 | BAT | bidirectional | Battery connection point to the positive terminal of the battery pack, with the internal BATFET and current sensing between SYS and BAT; connect 10 µF close to the pin. |
| 15 | SYS | power_out | Converter output connection point with internal current sensing network between SYS and BAT; connect a 20 µF capacitor close to the pin. |
| 16 | SYS | power_out | Converter output connection point with internal current sensing network between SYS and BAT; connect a 20 µF capacitor close to the pin. |
| 17 | GND | power_in | Ground pin. |
| 18 | GND | power_in | Ground pin. |
| 19 | SW | power_out | Switching node output connected to the output inductor; connect the 0.047-µF bootstrap capacitor from SW to BTST. |
| 20 | SW | power_out | Switching node output connected to the output inductor; connect the 0.047-µF bootstrap capacitor from SW to BTST. |
| 21 | BTST | passive | PWM high-side driver positive supply, internally connected to the bootstrap diode cathode; connect a 0.047-µF bootstrap capacitor from SW to BTST. |
| 22 | REGN | power_out | LSFET driver and internal supply output, connected internally to the bootstrap diode anode; connect a 4.7-µF (10-V rating) ceramic capacitor to GND close to the IC. |
| 23 | PMID | passive | Connected to the drain of the reverse blocking MOSFET (RBFET) and the drain of HSFET; place a 10-µF ceramic capacitor from PMID to GND. |
| 24 | VAC | input | Charge input voltage sense; this pin must be connected to the VBUS pin. |
| 25 | EP | passive | Exposed pad (from the footprint; not named in the datasheet pin table). |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Texas Instruments |
| Package | WQFN-24-EP(4x4) |
| Category | Power Supply Chip |
| Pins | 25 |
Electrical characteristics
Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Voltage range VAC, VBUS (converter not switching) | -2 | 22 | V | with respect to GND | 7 | ||
| Voltage range BTST, PMID (converter not switching) | -0.3 | 22 | V | with respect to GND | 7 | ||
| Voltage range SW | -2 | 16 | V | with respect to GND | 7 | ||
| Voltage range BTST to SW | -0.3 | 7 | V | 7 | |||
| Voltage range D+, D- | -0.3 | 7 | V | with respect to GND | 7 | ||
| Voltage range REGN, TS, CE, BAT, SYS (converter not switching) | -0.3 | 7 | V | with respect to GND | 7 | ||
| Voltage range SDA, SCL, INT, /QON, STAT | -0.3 | 7 | V | with respect to GND | 7 | ||
| Voltage range PGND to GND | -0.3 | 0.3 | V | QFN package only | 7 | ||
| Output sink current STAT | 6 | mA | 7 | ||||
| Output sink current INT | 6 | mA | 7 | ||||
| Operating junction temperature | TJ | -40 | 150 | °C | 7 | ||
| Storage temperature | Tstg | -65 | 150 | °C | 7 | ||
| ESD HBM | V(ESD) | -2000 | 2000 | V | HBM, all pins | 7 | |
| ESD CDM | V(ESD) | -250 | 250 | V | CDM, all pins | 7 | |
| VBUS input voltage | VBUS | 3.9 | 13.5 | V | 7 | ||
| Input current (VBUS) | Iin | 3.25 | A | 7 | |||
| Output current (SW) | ISWOP | 3.25 | A | 7 | |||
| Battery voltage | VBATOP | 4.615 | V | 7 | |||
| Fast charging current | IBATOP | 3 | A | 7 | |||
| Discharging current (continuous) | IBATOP | 6 | A | 7 | |||
| Operating ambient temperature | TA | -40 | 85 | °C | 7 | ||
| Junction-to-ambient thermal resistance | RθJA | 35.6 | °C/W | RTW (WQFN) 24 pins | 8 | ||
| Junction-to-case (top) thermal resistance | RθJC(top) | 22.7 | °C/W | 8 | |||
| Junction-to-board thermal resistance | RθJB | 11.9 | °C/W | 8 | |||
| Junction-to-top characterization parameter | ΨJT | 0.2 | °C/W | 8 | |||
| Junction-to-board characterization parameter | ΨJB | 12 | °C/W | 8 | |||
| Junction-to-case (bottom) thermal resistance | RθJC(bot) | 2.6 | °C/W | 8 | |||
| Battery discharge current, HIZ, BATFET disabled | IBAT | 17 | 33 | µA | VBAT = 4.5 V, HIZ Mode and No VBUS, I2C disabled, BATFET Disabled. TJ < 85°C | 8 | |
| Battery discharge current, HIZ, BATFET enabled | IBAT | 58 | 85 | µA | VBAT = 4.5 V, HIZ Mode and No VBUS, I2C Disabled, BATFET Enabled. TJ < 85°C | 8 | |
| Input supply current HIZ 5 V | IVBUS_HIZ | 37 | 55 | µA | VVBUS = 5 V, High-Z Mode, No battery | 8 | |
| Input supply current HIZ 12 V | IVBUS_HIZ | 68 | 93 | µA | VVBUS = 12 V, High-Z Mode, No battery | 8 | |
| VBUS operating range | VBUS_OP | 3.9 | 13.5 | V | VVBUS rising | 8 | |
| VBUS for active I2C, no battery | VVAC_UVLOZ | 3.3 | 3.6 | V | VVAC rising | 8 | |
| REGN turn-on VAC threshold | VVAC_PRESENT | 3.65 | 3.9 | V | VVAC rising | 8 | |
| Sleep mode falling threshold | VSLEEP | 15 | 60 | 131 | mV | VAC falling | 8 |
| Sleep mode rising threshold | VSLEEPZ | 115 | 220 | 340 | mV | VAC rising | 8 |
| VAC 6.5-V overvoltage rising threshold | VVAC_OV_RISE | 6.1 | 6.4 | 6.7 | V | VAC rising; OVP (REG06[7:6]) = '01' | 9 |
| VAC 10.5-V overvoltage rising threshold | VVAC_OV_RISE | 10.35 | 10.9 | 11.5 | V | VAC rising, OVP (REG06[7:6]) = '10' | 9 |
| VAC 14-V overvoltage rising threshold | VVAC_OV_RISE | 13.5 | 14.2 | 14.85 | V | VAC rising, OVP (REG06[7:6]) = '11' | 9 |
| Battery depletion threshold falling | VBAT_DPL_FALL | 2.2 | 2.6 | V | VBAT falling | 9 | |
| Battery depletion threshold rising | VBAT_DPL_RISE | 2.34 | 2.86 | V | VBAT rising | 9 | |
| Bad adapter detection falling threshold | VBUSMIN_FALL | 3.75 | 3.9 | 4 | V | VBUS falling | 9 |
| System regulation voltage | VSYS_MIN | 3.5 | 3.68 | V | VVBAT < SYS_MIN[2:0] = 101, BATFET Disabled (REG07[5] = 1) | 9 | |
| Maximum DC system voltage output | VSYS_MAX | 4.4 | 4.45 | 4.48 | V | ISYS = 0 A, Q4 off, VVBAT≤ 4.400 V, VVBAT > VSYSMIN = 3.5V | 9 |
| RBFET on-resistance | RON(RBFET) | 45 | mΩ | -40°C≤ TA ≤ 125°C | 9 | ||
| HSFET on-resistance | RON(HSFET) | 62 | mΩ | VREGN = 5 V , -40°C≤ TA ≤ 125°C | 9 | ||
| LSFET on-resistance | RON(LSFET) | 71 | mΩ | VREGN = 5 V , -40°C≤ TA ≤ 125°C | 9 | ||
| SYS-BAT MOSFET on-resistance | RON(BAT-SYS) | 19.5 | 24 | mΩ | QFN package, BAT to SYS, VBAT = 4.2V, TJ = 25°C | 9 | |
| SYS-BAT MOSFET on-resistance | RON(BAT-SYS) | 19.5 | 30 | mΩ | QFN package, BAT to SYS, VBAT = 4.2V, TJ = -40 - 125°C | 9 | |
| Charge voltage program range | VBATREG_RANGE | 3.847 | 4.615 | V | 9 | ||
| Charge voltage setting 4.20 V | VBATREG | 4.178 | 4.2 | 4.22 | V | VREG (REG04[7:3]) = 4.20 V (01011), -40 ≤ TJ ≤ 85°C | 10 |
| Charge voltage setting 4.343 V | VBATREG | 4.321 | 4.343 | 4.365 | V | VREG (REG04[7:3]) = 4.343 V (01111), -40 ≤ TJ ≤ 85°C | 10 |
| Charge voltage setting 4.391 V | VBATREG | 4.373 | 4.391 | 4.407 | V | VREG (REG04[7:3]) = 4.391 V (10001), -40 ≤ TJ ≤ 85°C | 10 |
| Charge current regulation range | ICHG_REG_RANGE | 0 | 3000 | mA | 10 | ||
| Charge current regulation 240 mA | ICHG_REG | 0.216 | 0.24 | 0.264 | A | ICHG = 240 mA, VVBAT = 3.1V or VVBAT = 3.8 V | 10 |
| Charge current regulation 720 mA | ICHG_REG | 0.685 | 0.72 | 0.761 | A | ICHG = 720 mA, VVBAT = 3.1 V or VVBAT = 3.8 V | 10 |
| Charge current regulation 1.38 A | ICHG_REG | 1.311 | 1.38 | 1.449 | A | ICHG = 1.38 A, VVBAT = 3.1 V or VVBAT = 3.8 V | 10 |
| Charge current accuracy 720 mA / 1.38 A | ICHG_REG_ACC | -5 | 5 | % | ICHG = 720 mA or ICHG = 1.38 A, VVBAT = 3.1 V or VVBAT = 3.8 V | 10 | |
| Battery LOWV falling threshold | VBATLOWV_FALL | 2.7 | 2.8 | 2.9 | V | ICHG = 240 mA | 10 |
| Battery LOWV rising threshold | VBATLOWV_RISE | 3 | 3.12 | 3.24 | V | Pre-charge to fast charge | 10 |
| Precharge current regulation | IPRECHG | 153 | 171 | 189 | mA | IPRECHG[3:0] = '0010' = 180 mA | 10 |
| Termination current regulation | ITERM | 150 | 180 | 216 | mA | ICHG > 780 mA, ITERM[3:0] = '0010' = 180 mA, VVBAT = 4.208 V | 10 |
| Termination current regulation | ITERM | 162 | 180 | 192 | mA | ICHG ≤ 780 mA, ITERM[3:0] = '0010' = 180 mA | 10 |
| Battery short voltage falling | VSHORT | 1.85 | 2 | 2.15 | V | VVBAT falling | 10 |
| Battery short voltage rising | VSHORTZ | 2.15 | 2.25 | 2.35 | V | VVBAT rising | 10 |
| Battery short current | ISHORT | 70 | 90 | 110 | mA | VVBAT < VSHORTZ | 10 |
| Recharge threshold below VBAT_REG | VRECHG | 90 | 120 | 150 | mV | VBAT falling, REG04[0] = 0 | 10 |
Materials and finish
As the datasheet states them (page.json metadata.appearance; the 3D model's colours follow it).
| Part | Material | Colour / plating | Datasheet says | Page |
|---|---|---|---|---|
| contacts | copper | 1. Place input capacitor as close as possible to PMID pin and GND pin connections and use shortest copper | 54 |
CAD (KiCad official)
- Symbol:
BQ25601DRTWR - Footprint:
Package_DFN_QFN:QFN-24-1EP_4x4mm_P0.5mm_EP2.6x2.6mm - 3D model: WQFN-24-EP(4x4) (KiCad packages3D, STEP)
- 3D model files:
bq25601drtwr-etched.step/bq25601drtwr-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);bq25601drtwr.step/bq25601drtwr.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: Texas Instruments datasheet (66 pp, sha256
4420f41c6497a003, retrieved 2026-10-22, tier: lcsc) - Datasheet language: Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
- Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-sonnet-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).