# BQ25505RGRR

**Texas Instruments** · Power Management Specialized - PMIC · VQFN-20-EP(3.5x3.5)

BQ25505RGRR from Texas Instruments, in a VQFN-20-EP(3.5x3.5). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

## Pinout

| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | VSS | power_in | General ground connection for the device; place the VIN_DC capacitor (at least 4.7 µF) and VSTOR capacitors close to this pin. |
| 2 | VIN_DC | power_in | DC voltage input from energy harvesters (0.1 V to 5.1 V recommended); connect at least a 4.7-µF capacitor as close as possible between this pin and pin 1. |
| 3 | VOC_SAMP | input | Sampling pin for the MPPT network; connect to VSTOR to sample at 80% of source open-circuit voltage, to GND for 50%, or to the mid-point of an external divider between VIN_DC and GND. |
| 4 | VREF_SAMP | passive | Connect a 0.01-µF low-leakage capacitor from this pin to GND to store the voltage to which VIN_DC will be regulated, provided by the MPPT sample circuit. |
| 5 | EN | input | Active-low digital programming input for enabling/disabling the IC; connect to GND to enable the IC. |
| 6 | NC | unconnected | Connect to VSS via the IC's PowerPad. |
| 7 | VBAT_OV | input | Connect to the mid-point of the external resistor divider between VRDIV and GND for setting the VSTOR = VBAT_SEC overvoltage threshold. |
| 8 | VRDIV | power_out | Biasing voltage to which the high side of the resistor divider networks is connected. |
| 9 | VB_SEC_ON | output | Active-low push-pull driver for the secondary (rechargeable) energy storage PMOS FET; leave floating if not used. |
| 10 | VB_PRI_ON | output | Active-low push-pull driver for the primary (nonrechargeable) energy storage PMOS FET; leave floating if not used. |
| 11 | OK_HYST | input | Connect to the mid-point of the external resistor divider between VRDIV and GND for setting the VBAT_OK hysteresis threshold; connect to GND if not used. |
| 12 | OK_PROG | input | Connect to the mid-point of the external resistor divider between VRDIV and GND for setting the VBAT_OK threshold; connect to GND if not used. |
| 13 | VBAT_OK | output | Digital battery-good indicator output internally referenced to the VSTOR voltage; leave floating if not used. |
| 14 | VBAT_PRI | input | Primary (nonrechargeable) energy storage element high-impedance sense input; leave floating if not used. |
| 15 | VSS | power_in | Signal ground connection for the device. |
| 16 | NC | unconnected | Connect to ground using the IC's PowerPad. |
| 17 | NC | unconnected | Connect to ground using the IC's PowerPad. |
| 18 | VBAT_SEC | bidirectional | Connect a secondary (rechargeable) storage element with at least 100 µF of equivalent capacitance to this pin. |
| 19 | VSTOR | power_out | Output of the boost charger, typically connected to the system load; connect at least a 4.7-µF capacitor in parallel with a 0.1-µF capacitor close to this pin and pin 1 (VSS). |
| 20 | LBOOST | passive | Inductor connection for the boost charger switching node; connect a 22-µH inductor between this pin and pin 2 (VIN_DC). |
| 21 | EP | passive | Exposed pad (from the footprint; not named in the datasheet pin table). |

## Key specifications

| Parameter | Value |
|---|---|
| Manufacturer | Texas Instruments |
| Package | VQFN-20-EP(3.5x3.5) |
| Category | Power Management ICs |
| Pins | 21 |

## Electrical characteristics

Limits as printed in the datasheet (page.json `metadata.characteristics` carries them as data).

| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| DC input voltage into VIN_DC | VIN(DC) | 100 |  | 5100 | mV | Cold-start completed | 7 |
| Cycle-by-cycle current limit of charger | ICHG(CBC_LIM) |  | 230 | 285 | mA | 0.5V < VIN < 4.0 V; VSTOR = 4.2 V | 7 |
| Input power range for normal charging | PIN | 0.005 |  | 510 | mW | VBAT_OV > VSTOR > VSTOR_CHGEN | 7 |
| Minimum input voltage for cold start | VIN(CS) |  | 600 | 700 | mV | VBAT_SEC < VBAT_UV; VSTOR = 0 V; 0°C < TA < 85°C | 7 |
| VSTOR when cold start ends | VSTOR_CHGEN | 1.6 | 1.73 | 1.9 | V |  | 7 |
| Quiescent current, full operating mode | IQ |  | 325 | 400 | nA | EN = GND; VIN_DC = 0V; VSTOR = 2.1V; TJ = 25°C | 7 |
| Quiescent current, full operating mode | IQ |  |  | 700 | nA | EN = GND; VIN_DC = 0V; VSTOR = 2.1V; -40°C < TJ < 85°C | 7 |
| Quiescent current, ship mode | IQ |  | 1 | 5 | nA | EN = VBAT_SEC; VBAT_SEC = VBAT_PRI = 2.1 V; TJ = 25°C; VSTOR = VIN_DC = 0 V | 7 |
| Quiescent current, ship mode | IQ |  |  | 20 | nA | EN = VBAT_SEC; VBAT_SEC = VBAT_PRI = 2.1 V; -40°C < TJ < 85°C; VSTOR = VIN_DC = 0 V | 7 |
| VBAT_PRI leakage current | I-BATPRI(LEAK) |  | 1 | 5 | nA | EN = VBAT_SEC; VBAT_PRI = VBAT_SEC = 2.1 V; TJ = 25°C; VIN_DC = 0 V; VSTOR floating | 7 |
| VBAT_PRI leakage current | I-BATPRI(LEAK) |  |  | 20 | nA | VBAT_PRI = VBAT_SEC = 2.1 V; -40°C < TJ < 85°C; VIN_DC = 0 V; VSTOR floating | 7 |
| ON resistance of switch VBAT_SEC to VSTOR | RDS(ON)-BAT |  | 0.95 | 1.5 | Ω | VBAT_SEC = 4.2 V | 7 |
| Charger low-side switch ON resistance | RDS(ON)_CHG |  | 0.7 | 0.9 | Ω | VBAT_SEC = 4.2 V | 7 |
| Charger high-side switch ON resistance | RDS(ON)_CHG |  | 2.3 | 3 | Ω | VBAT_SEC = 4.2 V | 7 |
| Charger low-side switch ON resistance | RDS(ON)_CHG |  | 0.8 | 1 | Ω | VBAT_SEC = 2.1 V | 7 |
| Charger high-side switch ON resistance | RDS(ON)_CHG |  | 3.7 | 4.8 | Ω | VBAT_SEC = 2.1 V | 7 |
| Programmable overvoltage threshold range | VBAT_OV | 2.2 |  | 5.5 | V | VBAT_SEC increasing | 8 |
| Battery overvoltage hysteresis | VBAT_OV_HYST |  | 24 | 45 | mV | VBAT_SEC decreasing; VBAT_OV = 5.25V | 8 |
| Undervoltage threshold | VBAT_UV | 1.91 | 1.95 | 2 | V | VBAT_SEC decreasing | 8 |
| Battery undervoltage hysteresis | VBAT_UV_HYST |  | 15 | 32 | mV | VBAT_SEC increasing | 8 |
| Overall accuracy for VBAT_OV, VBAT_OK thresholds | VBAT_ACCURACY | -2 |  | 2 | % | Selected resistors are 0.1% tolerance | 8 |
| Internal reference for programmable thresholds | VBIAS | 1.205 | 1.21 | 1.217 | V | VSTOR ≥ VSTOR_CHGEN | 8 |
| Dead time between VB_SEC_ON and VB_PRI_ON | tDEAD |  | 5 | 8 | us | Specified by design | 8 |
| Minimum cold-start input power | PIN(CS) |  | 15 |  | µW | VSTOR < VSTOR(CHGEN) and VIN_DC clamped to VIN(CS); VBAT with 100 µF ceramic capacitor | 7 |
| Battery hot plug switch closing time | tBAT_HOT_PLUG |  | 50 |  | ms | Battery resistance = 300 Ω, Battery voltage = 3.3V | 7 |
| Maximum charger switching frequency | fSW |  | 1 |  | MHz |  | 7 |
| Thermal shutdown junction temperature | TTEMP_SD |  | 125 |  | °C | VBAT_OV > VSTOR > 1.8V | 7 |
| Time between MPPT samples | VOC_SAMPLE |  | 16 |  | s |  | 8 |
| MPPT sample settling time | VOC_STLG |  | 256 |  | ms | Device not switching | 8 |
| Regulation of VIN_DC during charging | VIN_REG |  | 10 |  | % | 0.5 V < VIN < 4 V; IIN(DC) = 10 mA | 8 |
| Input/output voltage pins |  | -0.3 |  | 5.5 | V | VIN_DC, VOC_SAMP, VREF_SAMP, VBAT_OV, VB_PRI_ON, VB_SEC_ON, VBAT_PRI, VBAT_SEC, VRDIV, OK_HYST, OK_PROG, VBAT_OK, VSTOR, LBST | 6 |
| Peak input power | PIN_PK |  |  | 510 | mW |  | 6 |
| Operating junction temperature range | TJ | -40 |  | 125 | °C |  | 6 |
| Storage temperature | Tstg | -65 |  | 150 | °C |  | 6 |
| ESD HBM | V(ESD) | -2000 |  | 2000 | V | Human body model per ANSI/ESDA/JEDEC JS-001 | 6 |
| ESD CDM | V(ESD) | -500 |  | 500 | V | Charged device model per JESD22-C101 | 6 |
| DC input voltage into VIN_DC | VIN(DC) | 0.1 |  | 5.1 | V | Maximum input power ≤ 400 mW. Cold start has been completed | 6 |
| Battery voltage range | VBAT_SEC, VBAT_PRI | 2 |  | 5.5 | V | VBAT_OV setting must be higher than VIN_DC | 6 |
| Input capacitance | CIN | 4.7 |  |  | µF |  | 6 |
| Storage capacitance | CSTOR | 4.7 |  |  | µF |  | 6 |
| Battery pin capacitance or equivalent battery capacity | CBAT | 100 |  |  | µF |  | 6 |
| Sampled reference storage capacitance | CREF | 9 | 10 | 11 | nF |  | 6 |
| Total resistance for MPPT reference | ROC1 + ROC2 | 18 | 20 | 22 | MΩ |  | 6 |
| Total resistance for VBAT_OK threshold | ROK1 + ROK2 + ROK3 | 11 | 13 | 15 | MΩ |  | 6 |
| Total resistance for VBAT_OV threshold | ROV1 + ROV2 | 11 | 13 | 15 | MΩ |  | 6 |
| Input inductance | L1 |  | 22 |  | µH |  | 6 |
| Operating junction temperature | TJ | -40 |  | 105 | °C |  | 6 |
| Junction-to-ambient thermal resistance | θJA |  | 34.6 |  | °C/W | RGR 20 pins | 7 |
| Junction-to-case (top) thermal resistance | θJCtop |  | 49 |  | °C/W | RGR 20 pins | 7 |
| Junction-to-board thermal resistance | θJB |  | 12.5 |  | °C/W | RGR 20 pins | 7 |
| Junction-to-top characterization parameter | ψJT |  | 0.5 |  | °C/W | RGR 20 pins | 7 |
| Junction-to-board characterization parameter | ψJB |  | 12.6 |  | °C/W | RGR 20 pins | 7 |
| Junction-to-case (bottom) thermal resistance | θJCbot |  | 1 |  | °C/W | RGR 20 pins | 7 |

## CAD (KiCad official)

- Symbol: `BQ25505RGRR`
- Footprint: `Package_DFN_QFN:QFN-20-1EP_3.5x3.5mm_P0.5mm_EP2x2mm`
- 3D model: VQFN-20-EP(3.5x3.5), generated from the KiCad footprint (body from the F.Fab outline, terminals on the pads, 0.9 mm nominal QFN height). Neither the vendor nor KiCad ships a 3D model for this package, so the dimensions are nominal, not the manufacturer's CAD (STEP)
- 3D model files: `bq25505rgrr-etched.step` / `bq25505rgrr-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `bq25505rgrr.step` / `bq25505rgrr.glb` are the bare package body.

## Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

- **Datasheet:** [Texas Instruments datasheet](https://www.ti.com/cn/lit/gpn/bq25505) (39 pp, sha256 `dd46bc016c8753e7`, retrieved 2026-10-30, tier: manufacturer)
- **Datasheet language:** Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.3`, primary `claude-sonnet-5-5` (text), consensus `claude-sonnet-5-5` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
- **CAD:** KiCad official libraries (CC-BY-SA 4.0).

[Datasheet PDF](docs/bq25505rgrr-datasheet.pdf)