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BQ25303JRTER
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Texas Instruments Battery Management ICs, WQFN-16-EP(3x3). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
3D Model
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Symbol & Footprint
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README
markdownBQ25303JRTER
Texas Instruments · Battery Management ICs · WQFN-16-EP(3x3)
BQ25303JRTER from Texas Instruments, in a WQFN-16-EP(3x3). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | VBUS | power_in | Charger input voltage with the input reverse-blocking MOSFET (RBFET) between VBUS and PMID; place a 2.2uF ceramic capacitor from VBUS to GND as close to the IC as possible. |
| 2 | REGN | power_out | Low-side FET driver positive supply output; connect a 2.2uF ceramic capacitor from REGN to GND placed close to the IC. |
| 3 | STAT | output | Open-drain charge status output connected to REGN through a current-limiting resistor and LED: low while charging, open when charge is complete or disabled via EN, blinking on a fault. |
| 4 | ICHG | input | Charge current program input; connect a 1% resistor RICHG to GND to set ICHG = KICHG/RICHG (KICHG = 40,000), no capacitor allowed, and charging stops with STAT blinking if the pin is shorted to GND or open. |
| 5 | POL | input | EN pin polarity select: floating gives active-low enable, grounded gives active-high enable. |
| 6 | EN | input | Device disable input: with POL floating the device is enabled when EN is floating or low and disabled when EN is high; with POL grounded it is enabled when EN is high and disabled when EN is low or floating. |
| 7 | TS | input | Battery temperature voltage input for an NTC thermistor (103AT-2 recommended) with divider resistors REGN-TS and TS-GND, and charging is suspended when TS voltage is out of range; if unused connect 10kΩ from REGN to TS and 10kΩ from TS to GND. |
| 8 | NC | unconnected | No connect; leave floating or connect to ground. |
| 9 | VSET | input | Battery charge voltage set input programmed by a pull-down resistor to GND: floating (>200kΩ) 4.1V, shorted to GND (<510Ω) 4.2V, 51kΩ 4.35V, 10kΩ 4.4V, with maximum capacitance of 50pF. |
| 10 | BAT | input | Battery voltage sense input connected to the battery pack positive terminal and inductor output node, with a 10µF capacitor recommended. |
| 11 | GND | power_in | Ground; connect directly to the thermal pad on the top layer, with a single-point connection between power ground and analog ground near the IC GND pin recommended. |
| 12 | GND | power_in | Ground; connect directly to the thermal pad on the top layer, with a single-point connection between power ground and analog ground near the IC GND pin recommended. |
| 13 | SW | passive | Switching node connected to the output inductor, internally the source of the N-channel HSFET and drain of the LSFET; connect a 0.047µF bootstrap capacitor between SW and BTST. |
| 14 | SW | passive | Switching node connected to the output inductor, internally the source of the N-channel HSFET and drain of the LSFET; connect a 0.047µF bootstrap capacitor between SW and BTST. |
| 15 | BTST | passive | High-side FET driver supply, internally connected to the cathode of the bootstrap diode; connect a 0.047µF bootstrap capacitor between SW and BTST. |
| 16 | PMID | passive | Connection to the drain of the reverse-blocking MOSFET (RBFET) and the drain of the high-side MOSFET (HSFET); place a 10µF ceramic capacitor from PMID to GND as close to the IC as possible. |
| 17 | Thermal Pad | power_in | Ground reference and thermal pad for heat conduction, to be connected externally to the ground plane through vias under the pad. |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Texas Instruments |
| Package | WQFN-16-EP(3x3) |
| Category | Power Supply Chip |
| Pins | 17 |
Electrical characteristics
Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| VBUS reverse current from BAT/SW | IVBUS_REVS | 0.07 | 3 | µA | VBAT = VSW = 4.5V, VBUS shorted to GND, TJ = -40°C to 85°C | 8 | |
| VBUS leakage in disable mode | IQ_VBUS_DIS | 3.5 | 4.25 | µA | VBUS = 5V, VBAT = 4V, charger disabled, /EN high, TJ = -40°C to 85°C | 8 | |
| BAT and SW leakage in HiZ mode | IQ_BAT_HIZ | 0.17 | 1 | µA | VBAT = VSW = 4.5V, VBUS floating, TJ = -40°C to 65°C | 8 | |
| VBUS operating range | VVBUS_OP | 4.1 | 17 | V | 8 | ||
| VBUS power-on reset | VVBUS_UVLOZ | 3 | 3.8 | V | VBUS rising | 8 | |
| VBUS to turn on REGN | VVBUS_LOWV | 3.8 | 3.9 | 4 | V | VBUS rising, REGN on, VBAT = 3.2V | 8 |
| Enter sleep mode threshold | VSLEEP | 30 | 60 | 100 | mV | VBUS falling, VBUS - VBAT, VVBUS_LOWV < VBAT < VBATREG | 8 |
| Exit sleep mode threshold | VSLEEPZ | 110 | 157 | 295 | mV | VBUS rising, VBUS - VBAT, VVBUS_LOWV < VBAT < VBATREG | 8 |
| VBUS overvoltage rising threshold | VVBUS_OVP_RISE | 17 | 17.4 | 17.8 | V | VBUS rising, converter stops switching | 8 |
| Blocking MOSFET on-resistance (Q1) | RDSON_Q1 | 40 | 65 | mΩ | VREGN = 5V | 8 | |
| High-side MOSFET on-resistance (Q2) | RDSON_Q2 | 50 | 82 | mΩ | VREGN = 5V | 8 | |
| Low-side MOSFET on-resistance (Q3) | RDSON_Q3 | 45 | 72 | mΩ | VREGN = 5V | 8 | |
| Charge voltage regulation, VSET floating | VBATREG | 4.08 | 4.1 | 4.12 | V | VSET pin floating, TJ = -40°C to +85°C | 9 |
| Charge voltage regulation, VSET 51kΩ | VBATREG | 4.328 | 4.35 | 4.371 | V | VSET pin with 51kΩ resistor, TJ = -40°C to +85°C | 9 |
| Charge voltage regulation, VSET 10kΩ | VBATREG | 4.378 | 4.4 | 4.422 | V | VSET pin with 10kΩ resistor, TJ = -40°C to +85°C | 9 |
| Charge voltage regulation, VSET grounded | VBATREG | 4.179 | 4.2 | 4.221 | V | VSET pin grounded, TJ = -40°C to +85°C | 9 |
| Charge current regulation 1.72A | ICHG | 1.55 | 1.72 | 1.89 | A | ICHG set to 1.72A, RICHG = 23.2kΩ | 9 |
| Charge current regulation 1.0A | ICHG | 0.9 | 1 | 1.1 | A | ICHG set to 1.0A, RICHG = 40.2kΩ | 9 |
| Charge current regulation 0.5A | ICHG | 0.4 | 0.5 | 0.6 | A | ICHG set to 0.5A, RICHG = 78.7kΩ | 9 |
| Termination current 1.72A | ITERM | 138 | 172 | 206 | mA | ICHG = 1.72A, 10% of ICHG, RICHG = 23.2kΩ | 9 |
| Termination current 1.0A | ITERM | 70 | 100 | 130 | mA | ICHG = 1.0A, 10% of ICHG, RICHG = 40.2kΩ | 9 |
| Termination current 0.5A | ITERM | 33 | 63 | 93 | mA | ICHG = 0.5A, ITERM = 63mA, RICHG = 78.7kΩ | 9 |
| Precharge current 1.72A | IPRECHG | 115 | 172 | 225 | mA | ICHG = 1.72A, 10% of ICHG, RICHG = 23.2kΩ | 9 |
| Precharge current 1.0A | IPRECHG | 50 | 100 | 150 | mA | ICHG = 1.0A, 10% of ICHG, RICHG = 40.2kΩ | 9 |
| Precharge current 0.5A | IPRECHG | 28 | 63 | 98 | mA | ICHG = 0.5A, RICHG = 78.7kΩ | 9 |
| VBAT short rising threshold | VBAT_SHORT_RISE | 2.05 | 2.2 | 2.35 | V | Short to precharge | 9 |
| VBAT short falling threshold | VBAT_SHORT_FALL | 1.85 | 2 | 2.15 | V | Precharge to short | 9 |
| Battery short current | IBAT_SHORT | 25 | 35 | 46 | mA | VBAT < VBAT_SHORT_FALL | 9 |
| VBAT_LOWV rising threshold | VBAT_LOWV_RISE | 2.9 | 3 | 3.1 | V | Precharge to fast charge | 9 |
| VBAT_LOWV falling threshold | VBAT_LOWV_FALL | 2.6 | 2.7 | 2.8 | V | Fast charge to precharge | 9 |
| Recharge hysteresis below VBATREG | VRECHG_HYS | 110 | 160 | 216 | mV | VBAT falling | 9 |
| Minimum input voltage regulation | VINDPM_MIN | 4 | 4.07 | 4.2 | V | VBAT = 3.5V, measured at PMID pin | 9 |
| Input voltage regulation | VINDPM | 4.15 | 4.28 | 4.41 | V | VBAT = 4V, measured at PMID pin, VINDPM = 1.044*VBAT + 0.125V | 9 |
| Input current regulation | IINDPM_3A | 3 | 3.35 | 3.7 | A | VBUS = 5V | 9 |
| Battery overvoltage rising threshold | VBAT_OVP_RISE | 101.9 | 103.5 | 105 | % | VBAT rising, as percentage of VBATREG | 9 |
| Battery overvoltage falling threshold | VBAT_OVP_FALL | 100 | 101.6 | 103.1 | % | VBAT falling, as percentage of VBATREG | 9 |
| Bootstrap refresh comparator threshold | VBTST_REFRESH | 2.7 | 3 | 3.3 | V | When LSFET refresh pulse is requested (VBTST - VSW), VBUS = 5V | 9 |
| HSFET cycle-by-cycle overcurrent limit threshold | IHSFET_OCP | 5.2 | 6.2 | 6.7 | A | 9 | |
| Junction temperature regulation accuracy | TREG | 111 | 120 | 133 | °C | 9 | |
| PWM switching frequency | FSW | 1.02 | 1.2 | 1.38 | MHz | SW node frequency | 10 |
| REGN LDO output voltage, VBUS 5V | VREGN | 4.2 | 5 | V | VVBUS = 5V, IREGN = 0mA to 16mA | 10 | |
| REGN LDO output voltage, VBUS 12V | VREGN | 4.5 | 5.4 | V | VVBUS = 12V, IREGN = 16mA | 10 | |
| ICHG pin regulation voltage | VICHG | 993 | 998 | 1003 | mV | 10 | |
| Programmable resistance on ICHG | RICHG | 11.7 | 250 | kΩ | VBUS = 5V, resistance decreasing | 10 | |
| RICHG threshold to clamp precharge and termination to 63mA | RICHG_HIGH | 60 | 65 | 70 | kΩ | RICHG > RICHG_HIGH | 10 |
| T1 (0°C) threshold, rising | VT1% | 72.68 | 73.5 | 74.35 | % | VTS rising, charger suspends charge, % of VREGN | 10 |
| T1 (0°C) threshold, falling | VT1% | 70.68 | 71.5 | 72.33 | % | VTS falling, % of VREGN | 10 |
| T2 (10°C) threshold, rising | VT2% | 67.7 | 68.5 | 69.5 | % | VTS rising, charge current reduced to 20% of ICHG, % of VREGN | 10 |
| T2 (10°C) threshold, falling | VT2% | 66.5 | 67.3 | 68.2 | % | VTS falling, % of VREGN | 10 |
| T3 (45°C) threshold, falling | VT3% | 46.35 | 47.25 | 48.15 | % | VTS falling, charge at 50% of ICHG and VREG = 4.1V above this temperature, % of VREGN | 10 |
| T3 (45°C) threshold, rising | VT3% | 47.35 | 48.25 | 49.15 | % | VTS rising, % of VREGN | 10 |
| T5 (60°C) threshold, falling | VT5% | 36.95 | 37.75 | 38.55 | % | VTS falling, charge suspended above this temperature, % of VREGN | 10 |
| T5 (60°C) threshold, rising | VT5% | 37.95 | 38.75 | 39.55 | % | VTS rising, % of VREGN | 10 |
| Fast charge safety timer | tSAFETY_FAST | 15 | 20 | 24 | hr | Fast charge safety timer, 20 hour | 10 |
| Precharge safety timer | tSAFETY_PRE | 1.5 | 2 | 2.5 | hr | Precharge safety timer | 11 |
| Input low threshold | VILO | 0.4 | V | Falling | 10 | ||
| Input high threshold | VIH | 1.3 | V | Rising | 10 | ||
| High-level leakage current on EN pin | IBIAS | 1 | µA | EN pin pulled up to 1.8V | 10 | ||
| VBUS voltage (converter not switching) | VBUS | -2 | 28 | V | Converter not switching, relative to GND | 7 | |
| PMID voltage (converter not switching) | PMID | -0.3 | 28 | V | Converter not switching, relative to GND | 7 | |
| SW voltage | SW | -2 | 20 | V | Relative to GND; -3V for 10ns | 7 | |
| BTST voltage | BTST | -0.3 | 25.5 | V | Relative to GND | 7 | |
| BAT voltage | BAT | -0.3 | 11 | V | Relative to GND | 7 | |
| REGN voltage | REGN | -0.3 | 5.5 | V | Relative to GND | 7 | |
| VSET voltage | VSET | -0.3 | 11 | V | Relative to GND | 7 | |
| ICHG, REGN, TS, STAT, POL, EN voltage | -0.3 | 5.5 | V | Relative to GND | 7 | ||
| BTST to SW voltage | -0.3 | 5.5 | V | 7 | |||
| Output sink current STAT | 6 | mA | 7 | ||||
| Output sink current REGN | 16 | mA | 7 | ||||
| Operating junction temperature | TJ | -40 | 150 | °C | 7 | ||
| Storage temperature | Tstg | -65 | 150 | °C | 7 | ||
| ESD HBM | V(ESD) | -2000 | 2000 | V | HBM per ANSI/ESDA/JEDEC JS-001, all pins | 7 | |
| ESD CDM | V(ESD) | -250 | 250 | V | CDM per JEDEC JESD22-C101, all pins | 7 | |
| Battery voltage | VBAT | 4.4 | V | 7 | |||
| Input current | IVBUS | 3 | A | 7 | |||
| Output current (SW) | ISW | 3 | A | 7 | |||
| Ambient temperature | TA | -40 | 85 | °C | 7 | ||
| Recommended inductance, VVBUS_MAX < 6.2V | L | 1 | µH | VVBUS_MAX < 6.2V | 7 | ||
| Recommended inductance, VVBUS_MAX > 6.2V | L | 2.2 | µH | VVBUS_MAX > 6.2V | 7 | ||
| Recommended capacitance on VBUS | CVBUS | 2.2 | µF | 7 | |||
| Recommended capacitance on PMID | CPMID | 10 | µF | 7 | |||
| Recommended capacitance on BAT | CBAT | 10 | µF | 7 | |||
| Junction-to-ambient thermal resistance | RθJA | 45.8 | °C/W | JEDEC, RTE 16-pin | 8 | ||
| Junction-to-case (top) thermal resistance | RθJC(top) | 48.5 | °C/W | 8 | |||
| Junction-to-board thermal resistance | RθJB | 19 | °C/W | 8 | |||
| Junction-to-top characterization parameter | ΨJT | 1.3 | °C/W | 8 | |||
| Junction-to-board characterization parameter | ΨJB | 19 | °C/W | 8 | |||
| Junction-to-case (bottom) thermal resistance | RθJC(bot) | 7.9 | °C/W | 8 | |||
| Thermal shutdown rising threshold | TSHUT | 150 | °C | Temperature increasing | 10 | ||
| Maximum PWM duty cycle | DMAX | 97 | % | 10 |
CAD (KiCad official)
- Symbol:
BQ25303JRTER - Footprint:
Package_DFN_QFN:QFN-16-1EP_3x3mm_P0.5mm_EP1.7x1.7mm - 3D model: WQFN-16-EP(3x3) (KiCad packages3D, STEP)
- 3D model files:
bq25303jrter-etched.step/bq25303jrter-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);bq25303jrter.step/bq25303jrter.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: Texas Instruments datasheet (38 pp, sha256
480dd7d29c5b6011, retrieved 2026-10-22, tier: lcsc) - Datasheet language: Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
- Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-sonnet-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).