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Name	Last commit message	Last updated
docs	Publish 0.1.0 · Ray	21d ago
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bq24725rgrr-etched.glb	bq24725rgrr: etched from the flattened plain STEP (service-occt 1.6.0, from the plain STEP) · Ray	17d ago
bq24725rgrr-etched.step	bq24725rgrr: etched from the flattened plain STEP (service-occt 1.6.0, from the plain STEP) · Ray	17d ago
bq24725rgrr-hero.glb	bq24725rgrr: etched from the flattened plain STEP (service-occt 1.6.0, from the plain STEP) · Ray	17d ago
bq24725rgrr-hero.overlay.json	bq24725rgrr: etched from the flattened plain STEP (service-occt 1.6.0, from the plain STEP) · Ray	17d ago
bq24725rgrr.glb	plain STEP: one free product with face colours (generated model was nested; tscircuit read it white) · Ray	17d ago
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bq24725rgrr.lbr	Publish 0.1.0 · Ray	21d ago
bq24725rgrr.step	plain STEP: one free product with face colours (generated model was nested; tscircuit read it white) · Ray	17d ago
package.json	bq24725rgrr: etched from the flattened plain STEP (service-occt 1.6.0, from the plain STEP) · Ray	17d ago
page.json	bq24725rgrr: etched from the flattened plain STEP (service-occt 1.6.0, from the plain STEP) · Ray	17d ago
README.md	Publish 0.1.0 · Ray	21d ago

BQ24725RGRR

Texas Instruments · Battery Management · VQFN-20-EP(3.5x3.5)

BQ24725RGRR from Texas Instruments, in a VQFN-20-EP(3.5x3.5). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin	Name	Type	Function
1	ACN	input	Input current sense resistor negative input; place optional 0.1 µF to GND for common-mode filtering and 0.1 µF from ACN to ACP for differential filtering.
2	ACP	input	Input current sense resistor positive input; place 0.1 µF to GND for common-mode filtering and 0.1 µF from ACN to ACP for differential filtering.
3	CMSRC	passive	ACDRV charge pump source input; connect via a 4 kΩ resistor to the common source of ACFET (Q1) and RBFET (Q2) to limit inrush current.
4	ACDRV	output	Charge pump output driving ACFET and RBFET, 6 V above CMSRC when ACDET is 2.4 V to 3.15 V, VCC is above UVLO and VCC is 275 mV above SRN; use a 4 kΩ resistor to the gates.
5	ACOK	output	AC adapter detection open-drain output, pulled high by an external 10 kΩ pull-up when ACDET is 2.4 V to 3.15 V, VCC is above UVLO and 275 mV above SRN, otherwise pulled low.
6	ACDET	input	Adapter detection input set by a resistor divider from adapter to GND; above 0.6 V with VCC above UVLO enables REGN LDO, ACOK comparator and IOUT.
7	IOUT	output	Buffered adapter or charge current output selectable by ChargeOption(), 20 times the sense resistor differential voltage; place 100 pF or less decoupling capacitor to GND.
8	SDA	bidirectional	SMBus open-drain data I/O; connect to host SMBus data line with a 10 kΩ pull-up.
9	SCL	input	SMBus open-drain clock input; connect to host SMBus clock line with a 10 kΩ pull-up.
10	ILIM	input	Charge current limit input set by divider from 3.3 V rail; control disabled above 1.6 V, charge disabled below 75 mV and enabled above 105 mV.
11	BATDRV	output	Charge pump output driving BATFET, 6 V above SRN to turn on and equal to SRN to turn off; use a 4 kΩ resistor to the gate.
12	SRN	input	Charge current sense resistor negative input and battery voltage sense; connect through a 7.5 Ω resistor with 0.1 µF to GND for filtering.
13	SRP	input	Charge current sense resistor positive input; connect through a 10 Ω resistor with 0.1 µF differential filter capacitor across the sense resistor.
14	GND	power_in	IC ground; connect to analog ground plane and to power ground only through the PowerPAD underneath the IC.
15	LODRV	output	Low side power MOSFET driver output; connect to the low side n-channel MOSFET gate.
16	REGN	power_out	6 V linear regulator output supplied from VCC, active when ACDET is above 0.6 V and VCC is above UVLO; connect a 1 µF ceramic capacitor to GND.
17	BTST	power_in	High side MOSFET driver power supply; connect 0.047 µF capacitor to PHASE and a bootstrap Schottky diode from REGN.
18	HIDRV	output	High side power MOSFET driver output; connect to the high side n-channel MOSFET gate.
19	PHASE	passive	High side power MOSFET driver source; connect to the source of the high side n-channel MOSFET.
20	VCC	power_in	Input supply, diode OR from adapter or battery voltage; use 10 Ω resistor and 1 µF capacitor to ground as low pass filter to limit inrush current.
21	PowerPAD	power_in	Exposed pad beneath the IC; always solder to the board with vias to analog and power ground planes, star-connecting grounds and dissipating heat.

Key specifications

Parameter	Value
Manufacturer	Texas Instruments
Package	VQFN-20-EP(3.5x3.5)
Category	Power Management (PMIC)
Pins	21

CAD (KiCad official)

Symbol: BQ24725RGRR
Footprint: Package_DFN_QFN:QFN-20-1EP_3.5x3.5mm_P0.5mm_EP2x2mm
3D model: VQFN-20-EP(3.5x3.5), generated from the KiCad footprint (body from the F.Fab outline, terminals on the pads, 0.9 mm nominal QFN height). Neither the vendor nor KiCad ships a 3D model for this package, so the dimensions are nominal, not the manufacturer's CAD (STEP)
3D model files: bq24725rgrr-etched.step / bq24725rgrr-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); bq24725rgrr.step / bq24725rgrr.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

Datasheet: Texas Instruments datasheet (43 pp, sha256 b367d2c19449e12f, retrieved 2026-10-12, tier: lcsc)
Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF