component
BQ24616RGET
Public Made by Adomby adom
Texas Instruments Battery Management, VQFN-24(4x4). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
3D Model
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Symbol & Footprint
Schematic Symbol
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PCB Footprint
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Datasheet
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README
markdownBQ24616RGET
Texas Instruments · Battery Management · VQFN-24(4x4)
BQ24616RGET from Texas Instruments, in a VQFN-24(4x4). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | ACN | input | Adapter current-sense resistor, negative input; place 0.1-μF ceramic capacitor from ACN to ACP for differential-mode filtering and optional 0.1-μF capacitor from ACN to GND for common-mode filtering |
| 2 | ACP | input | Adapter current-sense resistor, positive input; place 0.1-μF ceramic capacitor from ACN to ACP for differential-mode filtering and 0.1-μF capacitor from ACP to GND for common-mode filtering |
| 3 | ACDRV | output | AC adapter-to-system MOSFET driver output; connect through 1-kΩ resistor to gate of ACFET P-channel MOSFET with asymmetrical internal gate drive and break-before-make logic with respect to BATDRV |
| 4 | CE | input | Charge-enable active-HIGH logic input; HI enables charge, LO disables charge, with internal 1-MΩ pulldown resistor |
| 5 | STAT1 | tri_state | Open-drain charge-status pin to indicate various charger operations |
| 6 | TS | input | Temperature qualification voltage input for battery pack negative-temperature-coefficient thermistor; program hot and cold temperature window with resistor-divider from VREF to TS to GND |
| 7 | TTC | input | Fast-charge safety timer and termination control; connect capacitor from this node to GND to set timer, LOW disables fast-charge timer and termination, HIGH disables fast-charge timer but allows termination |
| 8 | PG | tri_state | Open-drain power good status output; active-LOW when IC has valid VCC (not in UVLO or ACOV or SLEEP mode), active-HIGH when IC has invalid VCC |
| 9 | STAT2 | tri_state | Open-drain charge-status pin to indicate various charger operations |
| 10 | VREF | power_out | 3.3-V regulated voltage output; place 1-μF ceramic capacitor from VREF to GND pin close to IC for programming voltage and current regulation and TS threshold |
| 11 | ISET1 | input | Fast-charge current-set input; voltage on ISET1 pin programs fast-charge current regulation set-point, must be higher than 2 times the termination current to avoid early termination during VT1 and VT2 range |
| 12 | VFB | input | Output voltage analog feedback adjustment; connect output of resistive voltage divider from battery terminals to adjust output battery regulation voltage |
| 13 | SRN | bidirectional | Charge current-sense resistor, negative input; place 0.1-μF ceramic capacitor from SRN to SRP for differential-mode filtering and optional 0.1-μF capacitor from SRN to GND for common-mode filtering |
| 14 | SRP | bidirectional | Charge current-sense resistor, positive input; place 0.1-μF ceramic capacitor from SRN to SRP for differential-mode filtering and 0.1-μF capacitor from SRP to GND for common-mode filtering |
| 15 | ISET2 | input | Precharge and termination current-set input; voltage of ISET2 pin programs precharge current regulation set-point and termination current trigger point |
| 16 | ACSET | input | Adapter current-set input; voltage on ACSET pin programs input current-regulation set-point during dynamic power management (DPM) |
| 17 | GND | power_in | Low-current sensitive analog/digital ground; connect with thermal underneath the IC on PCB layout |
| 18 | REGN | output | PWM low-side driver positive 6-V supply output; connect 1-μF ceramic capacitor from REGN to GND pin close to IC and small-signal Schottky diode from REGN to BTST for bootstrap voltage |
| 19 | LODRV | output | PWM low-side driver output; connect to gate of low-side power MOSFET with short trace |
| 20 | PH | input | PWM high-side driver negative supply; connect to phase-switching node (junction of low-side MOSFET drain, high-side MOSFET source, and output inductor) |
| 21 | HIDRV | output | PWM high-side driver output; connect to gate of high-side power MOSFET with short trace |
| 22 | BTST | power_in | PWM high-side driver positive supply; connect 0.1-μF bootstrap capacitor from PH to BTST and bootstrap Schottky diode from REGN to BTST |
| 23 | BATDRV | output | Battery-to-system MOSFET driver output; gate drive for battery-to-system load BAT PMOS power FET to isolate system from battery with asymmetrical internal gate drive and break-before-make logic with respect to ACDRV |
| 24 | VCC | power_in | IC power positive supply; connect through 10-Ω resistor to common-source (diode-OR) point of high-side P-channel MOSFET and reverse-blocking power P-channel MOSFET, place 1-μF ceramic capacitor from VCC to GND pin close to IC |
| 25 | Thermal Pad | passive | Exposed pad (from the footprint; not named in the datasheet pin table). |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Texas Instruments |
| Package | VQFN-24(4x4) |
| Category | Power Management (PMIC) |
| Pins | 25 |
CAD (KiCad official)
- Symbol:
BQ24616RGET - Footprint:
Package_DFN_QFN:QFN-24-1EP_4x4mm_P0.5mm_EP2.6x2.6mm - 3D model: VQFN-24(4x4) (KiCad packages3D, STEP)
- 3D model files:
bq24616rget-etched.step/bq24616rget-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);bq24616rget.step/bq24616rget.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: Texas Instruments datasheet (43 pp, sha256
481c7492f39e1622, retrieved 2026-10-01, tier: lcsc) - Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-haiku-4-5-20251001(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).