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BQ24610RGET

Texas Instruments · Battery Management ICs · VQFN-24-EP(4x4)

BQ24610RGET from Texas Instruments, in a VQFN-24-EP(4x4). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 ACN input Adapter current-sense resistor negative input, with a 0.1-μF ceramic capacitor from ACN to ACP for differential-mode filtering and an optional 0.1-μF capacitor from ACN to GND for common-mode filtering.
2 ACP input Adapter current-sense resistor positive input, with a 0.1-μF ceramic capacitor from ACN to ACP for differential-mode filtering and a 0.1-μF capacitor from ACP to GND for common-mode filtering.
3 ACDRV output AC adapter-to-system MOSFET driver output, connected through a 1-kΩ resistor to the gates of the ACFET and reverse-blocking P-channel MOSFETs, with internal break-before-make logic with respect to BATDRV.
4 CE input Charge enable active-HIGH logic input, where HIGH enables charge and LOW disables it, with an internal 1-MΩ pulldown resistor.
5 STAT1 output Open-drain charge status output that indicates charger operation as defined in Table 2 (ON during charge in progress).
6 TS input Temperature qualification voltage input for a battery-pack NTC thermistor, with the hot and cold window programmed by a resistor divider from VREF to TS to GND; the absolute maximum rating is -0.3 V to 7 V.
7 TTC input Safety timer and termination control input, with a capacitor from TTC to GND setting the timer; when LOW the timer and termination are disabled, and when HIGH the timer is disabled but termination is allowed.
8 PG output Open-drain power-good status output that is active LOW when VCC is valid (not in UVLO, ACOV, or SLEEP mode) and active HIGH when VCC is invalid.
9 STAT2 output Open-drain charge status output that indicates charger operation as defined in Table 2 (ON during charge complete).
10 VREF power_out 3.3-V regulated voltage output that requires a 1-μF ceramic capacitor to GND close to the IC and can be used to program voltage, current, and the TS threshold.
11 ISET1 input Fast-charge current-set input whose voltage programs the fast-charge current regulation set point; the absolute maximum rating is 3.6 V and the recommended maximum is 3.3 V.
12 VFB input Output voltage analog feedback input, fed from a resistive divider on the battery terminals to set the battery regulation voltage, with a series resistor required if the battery pack voltage may exceed 16 V.
13 SRN input Charge current-sense resistor negative input, with a 0.1-μF ceramic capacitor from SRN to SRP for differential-mode filtering and an optional 0.1-μF capacitor from SRN to GND for common-mode filtering.
14 SRP input Charge current-sense resistor positive input, with a 0.1-μF ceramic capacitor from SRN to SRP for differential-mode filtering and a 0.1-μF capacitor from SRP to GND for common-mode filtering.
15 ISET2 input Precharge and termination current-set input whose voltage programs the precharge current regulation set point and the termination current trigger point.
16 ACSET input Adapter current-set input whose voltage programs the input current regulation set point during Dynamic Power Management (DPM).
17 GND power_in Low-current sensitive analog and digital ground, to be connected to the thermal pad underneath the IC on the PCB.
18 REGN power_out PWM low-side driver positive 6-V supply output, requiring a 1-μF ceramic capacitor to GND close to the IC and a small-signal Schottky diode to BTST for the bootstrap.
19 LODRV output PWM low-side driver output, connected to the gate of the low-side power MOSFET with a short trace; the absolute maximum rating is -0.3 V to 7 V relative to GND.
20 PH passive PWM high-side driver negative supply, connected to the phase-switching node (low-side MOSFET drain, high-side MOSFET source, and output inductor); the recommended range is -2 V to 30 V.
21 HIDRV output PWM high-side driver output, connected to the gate of the high-side power MOSFET with a short trace; the recommended range with respect to GND is -0.3 V to 34 V.
22 BTST power_in PWM high-side driver positive supply, with a 0.1-μF bootstrap capacitor from PH to BTST and a bootstrap Schottky diode from REGN to BTST; the recommended range with respect to GND is -0.3 V to 34 V.
23 BATDRV output Battery-to-system MOSFET driver output, connected through a 1-kΩ resistor to the gate of the input BAT P-channel MOSFET, with internal break-before-make logic with respect to ACDRV.
24 VCC power_in IC power positive supply, connected through a 10-Ω resistor to the diode-OR common-source point, with a 1-μF ceramic capacitor from VCC to the GND pin close to the IC; the BQ24610 recommended range is -0.3 V to 28 V.
25 Thermal pad passive Exposed pad (from the footprint; not named in the datasheet pin table).

Key specifications

Parameter Value
Manufacturer Texas Instruments
Package VQFN-24-EP(4x4)
Category Power Supply Chip
Pins 25

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
VCC, ACP, ACN, SRP, SRN, BATDRV, ACDRV, CE, STAT1, STAT2, PG -0.3 33 V over operating free-air temperature range (unless otherwise noted) 5
PH -2 36 V over operating free-air temperature range (unless otherwise noted) 5
VFB -0.3 16 V over operating free-air temperature range (unless otherwise noted) 5
REGN, LODRV, ACSET, TS, TTC -0.3 7 V over operating free-air temperature range (unless otherwise noted) 5
BTST, HIDRV with respect to GND -0.3 39 V over operating free-air temperature range (unless otherwise noted) 5
VREF, ISET1, ISET2 -0.3 3.6 V over operating free-air temperature range (unless otherwise noted) 5
Maximum difference voltage ACP-ACN, SRP-SRN -0.5 0.5 V 5
Junction temperature TJ -40 155 °C 5
Storage temperature Tstg -55 155 °C 5
BQ24610: VCC, ACP, ACN, SRP, SRN, BATDRV, ACDRV, CE, STAT1, STAT2, PG -0.3 28 V 6
PH -2 30 V 6
VFB -0.3 14 V 6
REGN, LODRV, ACSET, TS, TTC -0.3 6.5 V 6
BTST, HIDRV with respect to GND -0.3 34 V 6
ISET1, ISET2 -0.3 3.3 V 6
Maximum difference voltage ACP-ACN, SRP-SRN -0.2 0.2 V 6
Junction temperature (recommended) TJ 0 125 °C 6
VCC input voltage operating range (610) VVCC_OP 5 28 V 7
Total battery discharge current (sum of currents into VCC, BTST, PH, ACP, ACN, SRP, SRN, VFB) IBAT 15 μA VFB ≤ 2.1 V; VVCC < VSRN, VVCC > VUVLO (SLEEP) 7
Battery discharge current (sum of currents into BTST, PH, SRP, SRN, VFB) 5 μA VFB ≤ 2.1 V; VVCC > VSRN, VVCC > VUVLO, CE = LOW 7
Battery discharge current (sum of currents into BTST, PH, SRP, SRN, VFB), charge done 5 μA VFB ≤ 2.1 V; VVCC > VSRN, VVCC > VVCCLOW, CE = HIGH, charge done 7
Adapter supply current (current into VCC, ACP, ACN pin), IC quiescent IAC 1 1.5 mA VVCC > VSRN, VVCC > VUVLO, CE = LOW (IC quiescent current) 7
Adapter supply current (current into VCC, ACP, ACN pin), charge done IAC 2 5 mA VVCC > VSRN, VVCC >VVCCLOW, CE = HIGH, charge done 7
Adapter supply current (current into VCC, ACP, ACN pin), charging IAC 25 mA VVCC > VSRN, VVCC >VVCCLOW, CE = HIGH, charging, Qg_total = 20 nC 7
Charge voltage regulation accuracy -0.5 0.5 % TJ = 0°C to 85°C 7
Charge voltage regulation accuracy -0.7 0.7 % TJ = -40°C to 125°C 7
Leakage current into VFB pin IVFB 100 nA VFB = 2.1 V 7
SRP-SRN current-sense voltage range VIREG_CHG 100 mV VIREG_CHG = VSRP, VSRN 7
Charge current regulation accuracy -3 3 % VIREG_CHG = 40 mV 7
Charge current regulation accuracy -4 4 % VIREG_CHG = 20 mV 7
Charge current regulation accuracy -25 25 % VIREG_CHG = 5 mV 7
Charge current regulation accuracy -40 40 % VIREG_CHG = 1.5 mV (VSRN > 3.1 V) 7
Precharge current regulation accuracy -4 4 % VIREG_PRECH = 20 mV 7
Precharge current regulation accuracy -25 25 % VIREG_PRECH = 5 mV 7
Precharge current regulation accuracy -55 55 % VIREG_PRECH = 1.5 mV (VSRN < 3.1 V) 7
Termination current accuracy -4 4 % VITERM = 20 mV 8
Termination current accuracy -25 25 % VITERM = 5 mV 8
Termination current accuracy -45 45 % VITERM = 1.5 mV 8
Input current regulation accuracy -3 3 % VIREG_DPM = 40 mV 8
Input current regulation accuracy -4 4 % VIREG_DPM = 20 mV 8
Input current regulation accuracy -25 25 % VIREG_DPM = 5 mV 8
ACP-ACN current-sense voltage range VIREG_DPM 100 mV VIREG_DPM = VACP, VACN 8
AC undervoltage rising threshold VUVLO 3.65 3.85 4 V Measure on VCC 8
SLEEP falling threshold VSLEEP_FALL 40 100 150 mV VVCC, VSRN to enter SLEEP 8
ACN to SRN falling threshold VACN-SRN_FALL 100 200 310 mV VACN, VSRN to turn on BATFET 8
Precharge to fast-charge transition (LOWV threshold) VLOWV 1.534 1.55 1.566 V Measured on VFB pin, rising 8
AC overvoltage rising threshold on VCC (BQ24610) VACOV 31.04 32 32.96 V 9
Cold temperature rising threshold VLTF 72.5 73.5 74.5 % As Percentage to VVREF 9
Hot temperature rising threshold VHTF 36.2 37 37.8 % As Percentage to VVREF 9
VREF regulator voltage VVREF_REG 3.267 3.3 3.333 V VVCC > VUVLO, (0- to 35-mA load) 10
REGN regulator voltage VREGN_REG 5.7 6 6.3 V VVCC > 10 V, CE = HIGH, (0- to 40-mA load) 10
Precharge safety timer range 1440 1800 2160 s Precharge time before fault occurs 10
Fast charge safety timer range, with +/- 10% accuracy TCHARGE 1 10 h Tchg = CTTC × KTTC 10
Fast charge timer accuracy -10 10 % 0.01 μF ≤ CTTC ≤ 0.11 μF 10
PWM switching frequency 510 600 690 kHz 11
Junction-to-ambient thermal resistance RθJA 43 °C/W RGE [VQFN], 24 pins 6
Junction-to-case (top) thermal resistance RθJC(top) 54.3 °C/W RGE [VQFN], 24 pins 6
Junction-to-board thermal resistance RθJB 20 °C/W RGE [VQFN], 24 pins 6
Junction-to-case (bottom) thermal resistance RθJC(bot) 4 °C/W RGE [VQFN], 24 pins 6

Materials and finish

As the datasheet states them (page.json metadata.appearance; the 3D model's colours follow it).

Part Material Colour / plating Datasheet says Page
contacts copper 3. Place the inductor input terminal as close as possible to the switching MOSFET output terminal. Minimize the copper area of this trace to lower electrical and magnetic field radiation, but make the 34

CAD (KiCad official)

  • Symbol: BQ24610RGET
  • Footprint: Package_DFN_QFN:QFN-24-1EP_4x4mm_P0.5mm_EP2.6x2.6mm
  • 3D model: VQFN-24-EP(4x4) (KiCad packages3D, STEP)
  • 3D model files: bq24610rget-etched.step / bq24610rget-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); bq24610rget.step / bq24610rget.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Texas Instruments datasheet (45 pp, sha256 3ae7b6131566362b, retrieved 2026-10-30, tier: manufacturer)
  • Datasheet language: Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF