component
BQ24292IRGER
Public Made by Adomby adom
Texas Instruments Battery Management, VQFN-24-EP(4x4). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
Generated by kicad-footprint-generator · KiCad file format 20260206
| Name | Last updated |
|---|---|
| docs | 2d ago |
| viewers | 2d ago |
| bq24292irger-etched.glb | 2d ago |
| bq24292irger-etched.step | 2d ago |
| bq24292irger-hero.glb | 1d ago |
| bq24292irger-hero.overlay.json | 2d ago |
| bq24292irger.glb | 2d ago |
| bq24292irger.kicad_mod | 2d ago |
| bq24292irger.kicad_sym | 2d ago |
| bq24292irger.lbr | 2d ago |
| bq24292irger.step | 2d ago |
| package.json | 2d ago |
| page.json | 2d ago |
| README.md | 2d ago |
BQ24292IRGER
Texas Instruments · Battery Management · VQFN-24-EP(4x4)
BQ24292IRGER from Texas Instruments, in a VQFN-24-EP(4x4). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | VBUS | power_in | Charger input voltage with reverse block MOSFET to PMID; place 1µF ceramic capacitor from VBUS to PGND. |
| 2 | PSEL | input | Power source selection input; high indicates USB host source, low indicates adapter source. |
| 3 | PG | output | Open-drain power good indicator active low; asserts when input voltage is between UVLO and ACOV and current limit above 30mA. |
| 4 | STAT | output | Open-drain charge status output; low indicates charging in progress, high indicates charge complete or charge disabled. |
| 5 | SCL | input | I2C interface clock requiring 10kΩ pull-up resistor to logic rail. |
| 6 | SDA | bidirectional | I2C interface data requiring 10kΩ pull-up resistor to logic rail. |
| 7 | INT | output | Open-drain interrupt output sending active low 256µs pulse to host via 10kΩ pull-up resistor for charger status reporting. |
| 8 | OTG | input | USB current limit selection in buck mode (high=500mA, low=100mA) and active high boost mode enable pin. |
| 9 | CE | input | Active-low charge enable pin; charging enabled when CE=low and REG01[5:4]=01. |
| 10 | ILIM | input | Analog input for maximum input current limit with ILIM voltage at 1V regulating IINMAX=(1V/RILIM)×KILIM, minimum 500mA. |
| 11 | TS1 | input | Temperature qualification input #1; connect negative temperature coefficient thermistor with resistor divider from REGN to GND; charge suspends if out of range. |
| 12 | TS2 | input | Temperature qualification input #2; connect negative temperature coefficient thermistor with resistor divider from REGN to GND; charge suspends if out of range. |
| 13 | BAT | power_in | Battery positive terminal connection with internal BATFET connected to SYS; place 10µF capacitor closely to BAT pin. |
| 14 | BAT | power_in | Battery positive terminal connection with internal BATFET connected to SYS; place 10µF capacitor closely to BAT pin. |
| 15 | SYS | power_in | System output connection with internal BATFET connected to BAT; switch-mode converter maintains above minimum system voltage when battery falls below threshold. |
| 16 | SYS | power_in | System output connection with internal BATFET connected to BAT; switch-mode converter maintains above minimum system voltage when battery falls below threshold. |
| 17 | PGND | power_in | Power ground for high-current converter node internally connected to source of n-channel LSFET; connect directly to input/output capacitor ground. |
| 18 | PGND | power_in | Power ground for high-current converter node internally connected to source of n-channel LSFET; connect directly to input/output capacitor ground. |
| 19 | SW | output | Switching node connected to output inductor with internal connection to HSFET source and LSFET drain; connect 0.047µF bootstrap capacitor from SW to BTST. |
| 20 | SW | output | Switching node connected to output inductor with internal connection to HSFET source and LSFET drain; connect 0.047µF bootstrap capacitor from SW to BTST. |
| 21 | BTST | power_in | Bootstrap capacitor supply node for PWM high-side gate driver internally connected to bootstrap diode anode requiring 0.047µF capacitor from SW. |
| 22 | REGN | power_in | PWM gate driver supply output connected to bootstrap diode cathode; place 1µF capacitor to GND for VBUS>6V or 4.7µF for VBUS<6V. |
| 23 | PMID | output | Mid-point node connected to reverse-blocking MOSFET drain and HSFET drain; connect 1µF capacitor to PGND with remaining input capacitance from PMID to PGND. |
| 24 | VBUS | power_in | Charger input voltage with reverse block MOSFET to PMID; place 1µF ceramic capacitor from VBUS to PGND. |
| 25 | Thermal Pad | passive | Exposed pad (from the footprint; not named in the datasheet pin table). |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Texas Instruments |
| Package | VQFN-24-EP(4x4) |
| Category | Power Management (PMIC) |
| Pins | 25 |
CAD (KiCad official)
- Symbol:
BQ24292IRGER - Footprint:
Package_DFN_QFN:QFN-24-1EP_4x4mm_P0.5mm_EP2.6x2.6mm - 3D model: VQFN-24-EP(4x4) (KiCad packages3D, STEP)
- 3D model files:
bq24292irger-etched.step/bq24292irger-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);bq24292irger.step/bq24292irger.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: Texas Instruments datasheet (51 pp, sha256
bd2acdb8ad91052d, retrieved 2026-10-07, tier: lcsc) - Datasheet language: Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
- Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-haiku-4-5-20251001(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).