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Name	Last commit message	Last updated
docs	bq24253rger: re-etch, flat white mark read from pin 1 (service-occt 1.4.0) + chip hero · Ray	1mo ago
viewers	bq24253rger: viewers · Ray	1mo ago
bq24253rger-etched.fit.json	bq24253rger: re-etch, flat white mark read from pin 1 (service-occt 1.4.0) + chip hero · Ray	1mo ago
bq24253rger-etched.glb	bq24253rger: re-etch, flat white mark read from pin 1 (service-occt 1.4.0) + chip hero · Ray	1mo ago
bq24253rger-etched.step	bq24253rger: re-etch, flat white mark read from pin 1 (service-occt 1.4.0) + chip hero · Ray	1mo ago
bq24253rger.glb	Publish 0.1.0 · Ray	1mo ago
bq24253rger.kicad_mod	Publish 0.1.0 · Ray	1mo ago
bq24253rger.kicad_sym	Publish 0.1.0 · Ray	1mo ago
bq24253rger.lbr	Publish 0.1.0 · Ray	1mo ago
bq24253rger.step	Publish 0.1.0 · Ray	1mo ago
package.json	bq24253rger: component.models_3d pose record per STEP (Z-up, seated z=0, pad-centre origin, identity binding) · Ray	1mo ago
page.json	bq24253rger: component.models_3d pose record per STEP (Z-up, seated z=0, pad-centre origin, identity binding) · Ray	1mo ago
README.md	Initial commit: component/bq24253rger · Ray	1mo ago

BQ24253RGER

Texas Instruments · Battery Management · VQFN-24-EP(4x4)

BQ24253RGER from Texas Instruments, in a VQFN-24-EP(4x4). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin	Name	Type	Function
1	CE	input	Charge Enable Active-Low Input; logic high places charger in standby mode by disabling the battery FET.
2	D+	input	BC1.2 compatible D+ adapter detection input supporting DCP, SDP, CDP, Apple, and TomTom adapter detection.
3	D-	input	BC1.2 compatible D- adapter detection input supporting DCP, SDP, CDP, Apple, and TomTom adapter detection.
4	AGND	power_in	Analog Ground for QFN package only; connect to thermal pad and ground plane of circuit.
5	EN1	input	Input Current Limit Configuration Input; use EN1 with EN2 to control maximum input current and enable USB compliance per Table 1.
6	EN2	input	Input Current Limit Configuration Input; use EN2 with EN1 to control maximum input current and enable USB compliance per Table 1.
7	CHG	tri_state	Charge Status Open Drain Output; pulled low when charge cycle starts and remains low during charging; high impedance when complete or disabled.
8	PG	tri_state	Power Good Open Drain Output; pulled low when valid supply (VBAT+VSLP to VOVP) is connected to IN; high impedance otherwise.
9	TS	input	Battery Pack NTC Temperature Monitor Input; connect TS to center tap of resistor divider from LDO to GND with NTC from TS to GND for JEITA monitoring.
10	ISET	input	Charge Current Programming Input; connect resistor from ISET to GND to program fast charge current from 300mA to 2A.
11	BAT	bidirectional	Battery Connection carrying charge/discharge current; connect to positive battery terminal and bypass with >1μF capacitor.
12	BAT	bidirectional	Battery Connection carrying charge/discharge current; connect to positive battery terminal and bypass with >1μF capacitor.
13	SYS	power_out	System Power Output and SMPS voltage sense point; connect to system output at bulk capacitors and bypass locally with >20μF.
14	SYS	power_out	System Power Output and SMPS voltage sense point; connect to system output at bulk capacitors and bypass locally with >20μF.
15	PGND	power_in	Power Ground terminal; connect to ground plane of circuit.
16	PGND	power_in	Power Ground terminal; connect to ground plane of circuit.
17	SW	output	Buck Converter Switch Output; connect to switching side of external inductor for PWM converter operation.
18	SW	output	Buck Converter Switch Output; connect to switching side of external inductor for PWM converter operation.
19	IN	power_in	Input Power Supply from AC adapter or USB port (4.35V to 10.5V); bypass to PGND with >2μF ceramic capacitor.
20	PMID	output	Intermediate voltage node connection between blocking FET and high-side FET in buck converter.
21	BOOT	power_out	High-Side MOSFET Gate Driver Supply; connect 0.033μF ceramic capacitor (voltage rating >15V) from BOOT to SW for gate drive.
22	ILIM	input	Input Current Limit Programming Input; connect resistor from ILIM to GND to program input limit from 0.5A to 2A (short for 2A default).
23	VDPM	input	Input VIN_DPM Threshold Programming Input; connect resistor divider between IN and GND with VDPM at center tap (1.2V reference) for DPM setting (short for 4.68V default).
24	LDO	power_out	LDO regulated output providing up to 50mA at 4.9V when VUVLO < VIN <18V; bypass with 1μF ceramic capacitor.
25	EP	passive	Exposed pad (from the footprint; not named in the datasheet pin table).

Key specifications

Parameter	Value
Manufacturer	Texas Instruments
Package	VQFN-24-EP(4x4)
Category	Power Management (PMIC)
Pins	25

CAD (KiCad official)

Symbol: BQ24253RGER
Footprint: Package_DFN_QFN:QFN-24-1EP_4x4mm_P0.5mm_EP2.7x2.7mm
3D model: VQFN-24-EP(4x4) (KiCad packages3D, STEP)
3D model files: bq24253rger-etched.step / bq24253rger-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); bq24253rger.step / bq24253rger.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

Datasheet: Texas Instruments datasheet (58 pp, sha256 ec309ffe1d694e7f, retrieved 2026-09-27, tier: lcsc)
Datasheet language: Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
Extractor: parts-factory 2.0.0 / extract_pins 0.2, primary claude-haiku-4-5-20251001 (text), consensus claude-sonnet-4-6 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF