BQ24196RGER

@@ -53,7 +53,7 @@         "number": "1",         "name": "VBUS",         "type": "power_in",-        "description": "Charger Input Voltage with internal n-channel reverse block MOSFET (RBFET) connected between VBUS source and PMID; place 1-\u00b5F ceramic capacitor from VBUS to PGND close to IC."+        "description": "Charger Input Voltage with internal n-channel reverse block MOSFET (RBFET) connected between VBUS source and PMID; place 1-µF ceramic capacitor from VBUS to PGND close to IC."       },       {         "number": "2",@@ -65,31 +65,31 @@         "number": "3",         "name": "PG",         "type": "output",-        "description": "Open drain active low power good indicator; connect to pull-up rail via 10-k\u03a9 resistor; LOW indicates good input source when input voltage between UVLO and ACOV, above SLEEP mode threshold, and current limit above 30 mA."+        "description": "Open drain active low power good indicator; connect to pull-up rail via 10-kΩ resistor; LOW indicates good input source when input voltage between UVLO and ACOV, above SLEEP mode threshold, and current limit above 30 mA."       },       {         "number": "4",         "name": "STAT",         "type": "output",-        "description": "Open drain charge status output to indicate charger operation; connect to pull-up rail via 10-k\u03a9 resistor; LOW indicates charge in progress, HIGH indicates charge complete or disabled, blinking at 1 Hz for fault conditions."+        "description": "Open drain charge status output to indicate charger operation; connect to pull-up rail via 10-kΩ resistor; LOW indicates charge in progress, HIGH indicates charge complete or disabled, blinking at 1 Hz for fault conditions."       },       {         "number": "5",         "name": "SCL",         "type": "input",-        "description": "I2C Interface clock; connect SCL to logic rail through 10-k\u03a9 resistor; supports standard mode up to 100 kbits and fast mode up to 400 kbits."+        "description": "I2C Interface clock; connect SCL to logic rail through 10-kΩ resistor; supports standard mode up to 100 kbits and fast mode up to 400 kbits."       },       {         "number": "6",         "name": "SDA",         "type": "bidirectional",-        "description": "I2C Interface data; connect SDA to logic rail through 10-k\u03a9 resistor; open drain pin used for bidirectional communication."+        "description": "I2C Interface data; connect SDA to logic rail through 10-kΩ resistor; open drain pin used for bidirectional communication."       },       {         "number": "7",         "name": "INT",         "type": "output",-        "description": "Open-drain Interrupt Output; connect INT to logic rail via 10-k\u03a9 resistor; sends active low 256-us pulse to host to report charger device status and fault conditions."+        "description": "Open-drain Interrupt Output; connect INT to logic rail via 10-kΩ resistor; sends active low 256-us pulse to host to report charger device status and fault conditions."       },       {         "number": "8",@@ -107,7 +107,7 @@         "number": "10",         "name": "ILIM",         "type": "input",-        "description": "Input current limit selection pin; sets maximum input current limit by regulating ILIM voltage at 1V using resistor from ILIM pin to ground; INMAX=(1V/RILIM)\u00d7530; actual input current limit is lower value set by ILIM and I2C REG00[2:0]; minimum input current is 500 mA."+        "description": "Input current limit selection pin; sets maximum input current limit by regulating ILIM voltage at 1V using resistor from ILIM pin to ground; INMAX=(1V/RILIM)×530; actual input current limit is lower value set by ILIM and I2C REG00[2:0]; minimum input current is 500 mA."       },       {         "number": "11",@@ -125,7 +125,7 @@         "number": "13",         "name": "BAT",         "type": "power_in",-        "description": "Battery connection point to positive terminal of battery pack; internal BATFET connected between BAT and SYS; connect 10 \u00b5F capacitor closely to BAT pin."+        "description": "Battery connection point to positive terminal of battery pack; internal BATFET connected between BAT and SYS; connect 10 µF capacitor closely to BAT pin."       },       {         "number": "14",@@ -161,7 +161,7 @@         "number": "19",         "name": "SW",         "type": "output",-        "description": "Switching node connecting to output inductor; internally connected to source of n-channel HSFET and drain of n-channel LSFET; connect 0.047-\u00b5F bootstrap capacitor from SW to BTST."+        "description": "Switching node connecting to output inductor; internally connected to source of n-channel HSFET and drain of n-channel LSFET; connect 0.047-µF bootstrap capacitor from SW to BTST."       },       {         "number": "20",@@ -173,19 +173,19 @@         "number": "21",         "name": "BTST",         "type": "power_in",-        "description": "PWM high side driver positive supply; internally connected to anode of bootstrap diode; connect 0.047-\u00b5F bootstrap capacitor from SW to BTST."+        "description": "PWM high side driver positive supply; internally connected to anode of bootstrap diode; connect 0.047-µF bootstrap capacitor from SW to BTST."       },       {         "number": "22",         "name": "REGN",         "type": "power_in",-        "description": "PWM low side driver positive supply output; internally connected to cathode of bootstrap diode; connect 4.7-\u00b5F (10-V rating) ceramic capacitor from REGN to analog GND close to IC; also serves as bias rail for TS1 and TS2 pins."+        "description": "PWM low side driver positive supply output; internally connected to cathode of bootstrap diode; connect 4.7-µF (10-V rating) ceramic capacitor from REGN to analog GND close to IC; also serves as bias rail for TS1 and TS2 pins."       },       {         "number": "23",         "name": "PMID",         "type": "output",-        "description": "Connected to drain of reverse blocking MOSFET and drain of HSFET; given total input capacitance, connect 1-\u00b5F capacitor on VBUS to PGND and rest on PMID to PGND."+        "description": "Connected to drain of reverse blocking MOSFET and drain of HSFET; given total input capacitance, connect 1-µF capacitor on VBUS to PGND and rest on PMID to PGND."       },       {         "number": "24",@@ -234,6 +234,46 @@     "viewers": {       "symbol": "viewers/symbol.html",       "footprint": "viewers/footprint.html"-    }+    },+    "models_3d": [+      {+        "file": "bq24196rger.step",+        "role": "plain",+        "up": "Z",+        "units": "mm",+        "origin": "footprint origin = pad-pattern centre",+        "seat": "z = 0",+        "extents_mm": [+          4.0,+          4.0,+          0.77+        ],+        "zmin_mm": 0.0,+        "centre_offset_mm": 0.0,+        "footprint_binding": "identity",+        "sha256": "096fc110543e6d324c5120c2d38e3dca87a389da9b6fac234f1fe40856295ef4",+        "checked": "2026-10-07",+        "checked_by": "factory/step_pose.py (Z-up, origin, seat, binding)"+      },+      {+        "file": "bq24196rger-etched.step",+        "role": "eda",+        "up": "Z",+        "units": "mm",+        "origin": "footprint origin = pad-pattern centre",+        "seat": "z = 0",+        "extents_mm": [+          4.0,+          4.0,+          0.77+        ],+        "zmin_mm": 0.0,+        "centre_offset_mm": 0.0,+        "footprint_binding": "identity",+        "sha256": "fee50454730b7a4aca55eb7dfb22e0f12c10c43d896053e0fb480025975f888d",+        "checked": "2026-10-07",+        "checked_by": "factory/step_pose.py (Z-up, origin, seat, binding)"+      }+    ]   }-}\ No newline at end of file+}