component
BQ24190RGER
Public Made by Adomby adom
Texas Instruments Battery Management ICs, VQFN-24-EP(4x4). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
Generated by kicad-footprint-generator · KiCad file format 20260206
| Name | Last updated |
|---|---|
| docs | 3d ago |
| viewers | 3d ago |
| bq24190rger-etched.glb | 3d ago |
| bq24190rger-etched.step | 3d ago |
| bq24190rger-hero.glb | 3d ago |
| bq24190rger-hero.overlay.json | 3d ago |
| bq24190rger.glb | 3d ago |
| bq24190rger.kicad_mod | 3d ago |
| bq24190rger.kicad_sym | 3d ago |
| bq24190rger.lbr | 3d ago |
| bq24190rger.step | 3d ago |
| package.json | 3d ago |
| page.json | 3d ago |
| README.md | 3d ago |
BQ24190RGER
Texas Instruments · Battery Management ICs · VQFN-24-EP(4x4)
BQ24190RGER from Texas Instruments, in a VQFN-24-EP(4x4). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | VBUS | power_in | Charger input voltage, with the internal reverse-block MOSFET (RBFET) between VBUS and PMID; place a 1-µF ceramic capacitor from VBUS to PGND as close to the IC as possible. |
| 2 | D+ | input | Positive line of the USB data pair used for D+/D- USB host/charging port detection, including data contact detection (DCD) and primary detection in bc1.2. |
| 3 | D- | input | Negative line of the USB data pair used for D+/D- USB host/charging port detection, including data contact detection (DCD) and primary detection in bc1.2. |
| 4 | STAT | output | Open-drain charge status output, pulled up via 10 kΩ; LOW indicates charge in progress, HIGH indicates charge complete or disabled, and it blinks at 1 Hz on any fault in the bq24190. |
| 5 | SCL | input | I2C interface clock; connect to the logic rail through a 10-kΩ resistor. |
| 6 | SDA | bidirectional | I2C interface data; connect to the logic rail through a 10-kΩ resistor. |
| 7 | INT | output | Open-drain interrupt output, pulled up to a logic rail via 10 kΩ, that sends an active-low 256-µs pulse to the host to report charger status and faults. |
| 8 | OTG | input | USB current limit selection pin in buck mode (with USB host, High = 500 mA, Low = 100 mA) and active-high enable in boost mode when REG01[5:4] = 10. |
| 9 | CE | input | Active-low charge enable; charging is enabled when REG01[5:4] = 01 and CE = Low, and the pin must be pulled high or low. |
| 10 | ILIM | input | Sets the maximum input current limit by regulating ILIM at 1 V with a resistor to ground (IINMAX = (1V/RILIM) × 530); the minimum programmable input current is 500 mA. |
| 11 | TS1 | input | Temperature qualification voltage input #1 for an NTC thermistor, programmed with a resistor divider from REGN; charge suspends when either TS pin is out of range (103AT-2 recommended). |
| 12 | TS2 | input | Temperature qualification voltage input #2 for an NTC thermistor, programmed with a resistor divider from REGN; charge suspends when either TS pin is out of range (103AT-2 recommended). |
| 13 | BAT | power_in | Battery connection to the positive pack terminal, with the internal BATFET between BAT and SYS; connect a 10-µF capacitor close to the pin. |
| 14 | BAT | power_in | Battery connection to the positive pack terminal, with the internal BATFET between BAT and SYS; connect a 10-µF capacitor close to the pin. |
| 15 | SYS | power_out | System connection point with the internal BATFET between BAT and SYS; the converter keeps SYS above the minimum system voltage when the battery is low. |
| 16 | SYS | power_out | System connection point with the internal BATFET between BAT and SYS; the converter keeps SYS above the minimum system voltage when the battery is low. |
| 17 | PGND | power_in | Power ground for the high-current converter node, internally connected to the source of the n-channel LSFET; connect directly to the input and output capacitor grounds. |
| 18 | PGND | power_in | Power ground for the high-current converter node, internally connected to the source of the n-channel LSFET; connect directly to the input and output capacitor grounds. |
| 19 | SW | output | Switching node connecting to the output inductor, with a 0.047-µF bootstrap capacitor from SW to BTST. |
| 20 | SW | output | Switching node connecting to the output inductor, with a 0.047-µF bootstrap capacitor from SW to BTST. |
| 21 | BTST | power_in | PWM high-side driver positive supply, connected internally to the bootstrap diode anode; connect a 0.047-µF capacitor from SW to BTST. |
| 22 | REGN | power_out | PWM low-side driver positive supply output and bias rail for TS1/TS2; connect a 4.7-µF (10-V rating) ceramic capacitor to analog GND close to the IC. |
| 23 | PMID | power_out | Connected to the drain of the reverse blocking MOSFET and the HSFET; put 1 µF on VBUS to PGND and the remaining input capacitance on PMID to PGND. |
| 24 | VBUS | power_in | Charger input voltage, with the internal reverse-block MOSFET (RBFET) between VBUS and PMID; place a 1-µF ceramic capacitor from VBUS to PGND as close to the IC as possible. |
| 25 | EP | passive | Exposed pad (from the footprint; not named in the datasheet pin table). |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Texas Instruments |
| Package | VQFN-24-EP(4x4) |
| Category | Power Supply Chip |
| Pins | 25 |
Electrical characteristics
Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Input voltage | VIN | 3.9 | 17 | V | 6 | ||
| Input current | IIN | 3 | A | 6 | |||
| Output current (SYS) | ISYS | 4.5 | A | 6 | |||
| Battery voltage | VBAT | 4.4 | V | 6 | |||
| Fast charging current | IBAT | 4.5 | A | 6 | |||
| Operating free-air temperature | TA | -40 | 85 | °C | 6 | ||
| VBUS voltage | VBUS | -2 | 22 | V | 5 | ||
| PMID voltage | PMID | -0.3 | 22 | V | 5 | ||
| STAT voltage | STAT | -0.3 | 20 | V | 5 | ||
| BTST voltage | BTST | -0.3 | 26 | V | 5 | ||
| SW voltage | SW | -2 | 20 | V | 5 | ||
| BAT, SYS voltage | -0.3 | 6 | V | converter not switching | 5 | ||
| SDA, SCL, INT, OTG, ILIM, REGN, TS1, TS2, CE, D+, D- voltage | -0.3 | 7 | V | 5 | |||
| Output sink current INT, STAT | 6 | mA | 5 | ||||
| Junction temperature | TJ | -40 | 150 | °C | 5 | ||
| Storage temperature | Tstg | -65 | 150 | °C | 5 | ||
| Junction-to-ambient thermal resistance | RθJA | 32.2 | °C/W | RGE (24 pin) | 6 | ||
| Junction-to-case (top) thermal resistance | RθJCtop | 29.8 | °C/W | RGE (24 pin) | 6 | ||
| Junction-to-board thermal resistance | RθJB | 9.1 | °C/W | RGE (24 pin) | 6 | ||
| Junction-to-case (bottom) thermal resistance | RθJCbot | 2.2 | °C/W | RGE (24 pin) | 6 | ||
| Battery discharge current, BATFET disabled | IBAT | 12 | 20 | µA | High-Z Mode, or no VBUS, BATFET disabled (REG07[5] = 1), -40°C to 85°C | 6 | |
| Battery discharge current, BATFET enabled | IBAT | 32 | 55 | µA | High-Z Mode, or no VBUS, REG07[5] = 0, -40°C to 85°C | 6 | |
| Input supply current, 5 V High-Z | IVBUS | 15 | 30 | µA | VVBUS = 5 V, High-Z mode | 6 | |
| Input supply current, 17 V High-Z | IVBUS | 30 | 50 | µA | VVBUS = 17 V, High-Z mode | 6 | |
| Input supply current, not switching | IVBUS | 1.5 | 3 | mA | VVBUS > VUVLO, VVBUS > VBAT, converter not switching | 6 | |
| VBUS operating range | VVBUS_OP | 3.9 | 17 | V | 7 | ||
| Sleep mode falling threshold | VSLEEP | 35 | 80 | 120 | mV | VVBUS falling, VVBUS-VBAT | 7 |
| Sleep mode rising threshold | VSLEEPZ | 170 | 250 | 350 | mV | VVBUS rising, VVBUS-VBAT | 7 |
| VBUS over-voltage rising threshold | VACOV | 17.4 | 18 | V | VVBUS rising | 7 | |
| Battery depletion threshold | VBAT_DPL | 2.4 | 2.6 | V | VBAT falling | 7 | |
| Battery depletion rising hysteresis | VBAT_DPL_HY | 170 | 260 | mV | VBAT rising | 7 | |
| Typical system regulation voltage | VSYS_RANGE | 3.5 | 4.35 | V | Isys = 0 A, Q4 off, VBAT up to 4.2 V, REG01[3:1] = 101, VSYSMIN = 3.5 V | 7 | |
| System voltage output | VSYS_MIN | 3.55 | 3.65 | V | REG01[3:1] = 101, VSYSMIN = 3.5 V | 7 | |
| RBFET on-resistance | RON(RBFET) | 23 | 38 | mΩ | Measured between VBUS and PMID | 7 | |
| HSFET on-resistance | RON(HSFET) | 27 | 35 | mΩ | TJ = -40°C to 85°C | 7 | |
| HSFET on-resistance | RON(HSFET) | 27 | 45 | mΩ | TJ = -40°C to 125°C | 7 | |
| LSFET on-resistance | RON(LSFET) | 32 | 45 | mΩ | TJ = -40°C to 85°C | 7 | |
| LSFET on-resistance | RON(LSFET) | 32 | 48 | mΩ | TJ = -40°C to 125°C | 7 | |
| Charge voltage regulation accuracy | VBAT_REG_ACC | -0.5 | 0.5 | % | VBAT = 4.112 V and 4.208 V | 7 | |
| Fast charge current regulation accuracy | IICHG_REG_ACC | -4 | 4 | % | VBAT = 3.8 V, ICHG = 1792 mA, TJ = 25°C | 7 | |
| Fast charge current regulation accuracy | IICHG_REG_ACC | -7 | 7 | % | VBAT = 3.8 V, ICHG = 1792 mA, TJ = -20°C to 125°C | 7 | |
| Charge current with 20% option on | ICHG_20pct | 75 | 100 | 150 | mA | VBAT = 3.1 V, ICHG = 104 mA, REG02 = 03 | 7 |
| Battery LOWV falling threshold | VBATLOWV | 2.6 | 2.8 | 2.9 | V | Fast charge to precharge, REG04[1] = 1 | 7 |
| Battery LOWV rising threshold | VBATLOWV_HYST | 2.8 | 3 | 3.1 | V | Precharge to fast charge, REG04[1] = 1 | 7 |
| Precharge current regulation accuracy | IPRECHG_ACC | -20 | 20 | % | VBAT = 2.6 V, ICHG = 256 mA | 7 | |
| Termination current accuracy | ITERM_ACC | -20 | 20 | % | ITERM = 256 mA, ICHG = 960 mA | 7 | |
| BATFET on-resistance | RON_BATFET | 12 | 15 | mΩ | TJ = 25°C | 7 | |
| BATFET on-resistance | RON_BATFET | 12 | 20 | mΩ | TJ = -40°C to 125°C | 7 | |
| Input voltage regulation accuracy | VINDPM_REG_ACC | -2 | 2 | % | REG00[6:3] = 0110 (4.36 V) or 1011 (4.76 V) | 8 | |
| USB100 input current regulation limit | IUSB_DPM | 85 | 100 | mA | USB100, VBUS = 5 V, current pulled from SW | 8 | |
| USB500 input current regulation limit | IUSB_DPM | 440 | 500 | mA | USB500, VBUS = 5 V, current pulled from SW | 8 | |
| Input current regulation accuracy | IADPT_DPM | 1.35 | 1.5 | 1.65 | A | Typical input current of 1.5 A based on KLIM | 8 |
| ILIM current constant | KILIM | 435 | 485 | 530 | A x Ω | IIN = KILIM/RILIM, IINDPM = 1.5 A | 8 |
| PWM switching frequency | FSW | 1300 | 1500 | 1700 | kHz | 8 | |
| REGN LDO output voltage | VREGN | 5.6 | 6 | 6.4 | V | VVBUS = 10 V, IREGN = 40 mA | 9 |
| OTG output voltage accuracy | VOTG_REG_ACC | -2 | 2 | % | I(VBUS) = 0 | 9 | |
| Thermal shutdown rising temperature | TSHUT | 160 | °C | Temperature increasing | 8 |
Materials and finish
As the datasheet states them (page.json metadata.appearance; the 3D model's colours follow it).
| Part | Material | Colour / plating | Datasheet says | Page |
|---|---|---|---|---|
| contacts | copper | 1. Place input capacitor as close as possible to PMID pin and GND pin connections and use shortest copper | 41 |
CAD (KiCad official)
- Symbol:
BQ24190RGER - Footprint:
Package_DFN_QFN:QFN-24-1EP_4x4mm_P0.5mm_EP2.6x2.6mm - 3D model: VQFN-24-EP(4x4) (KiCad packages3D, STEP)
- 3D model files:
bq24190rger-etched.step/bq24190rger-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);bq24190rger.step/bq24190rger.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: Texas Instruments datasheet (53 pp, sha256
45b39a9199a8ba62, retrieved 2026-10-22, tier: manufacturer) - Datasheet language: Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
- Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-sonnet-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).