component
BQ24166RGET
Public Made by Adomby adom
Texas Instruments Battery Management, VQFN-24-EP(4x4). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
3D Model
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Symbol & Footprint
Schematic Symbol
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PCB Footprint
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Datasheet
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README
markdownBQ24166RGET
Texas Instruments · Battery Management · VQFN-24-EP(4x4)
BQ24166RGET from Texas Instruments, in a VQFN-24-EP(4x4). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | VDPM | input | Input Voltage Dynamic Power Management programming input; connect resistor divider from IN to GND with VDPM at center tap to program VIN-DPM threshold. |
| 2 | IUSB3 | input | USB input current limit programming input for USB3.0 standard. |
| 3 | IUSB2 | input | USB input current limit programming input for USB2.0 standard. |
| 4 | IUSB1 | input | USB input current limit programming input with USB2.0 and USB3.0 current limits available per Table 1. |
| 5 | ISET | input | Charge current programming input; connect resistor from ISET to GND to program fast charge current from 550mA to 2.5A. |
| 6 | DRV | power_out | Gate drive bias supply for internal MOSFETs; bypass to PGND with 1μF ceramic capacitor; capable of supplying up to 10mA to external loads. |
| 7 | PG | tri_state | Power good open drain output pulled low when valid supply between VBAT+VSLP and VOVP is connected to USB or IN; high impedance otherwise. |
| 8 | CHG | tri_state | Charge status open drain output pulled low when charge cycle starts and remains low while charging; high impedance when charging terminates. |
| 9 | TS | input | Battery pack NTC thermistor monitor input; connect to center tap of resistor divider from DRV to GND with thermistor to GND. |
| 10 | BGATE | output | External P-channel MOSFET gate connection for discharge path; pulled low during high impedance mode and when no input connected. |
| 11 | BAT | bidirectional | Battery positive terminal connection; additionally bypass to GND with at least 1μF capacitor. |
| 12 | BAT | bidirectional | Battery positive terminal connection; additionally bypass to GND with at least 1μF capacitor. |
| 13 | SYS | input | System voltage sense and charger FET connection; connect to system output at output bulk capacitors and bypass locally with at least 10μF. |
| 14 | SYS | input | System voltage sense and charger FET connection; connect to system output at output bulk capacitors and bypass locally with at least 10μF. |
| 15 | ILIM | input | IN input current limit programming input; connect resistor from ILIM to GND to program current limit from 1A to 2.5A; no effect on USB input. |
| 16 | PGND | power_in | Power ground terminal; connect to thermal pad and ground plane of the circuit. |
| 17 | PGND | power_in | Power ground terminal; connect to thermal pad and ground plane of the circuit. |
| 18 | SW | power_out | Inductor connection; connect to the switched side of the external inductor. |
| 19 | BOOT | passive | Boot capacitor connection; connect 0.01μF ceramic capacitor with voltage rating > 10V from BOOT to SW for high side MOSFET gate drive. |
| 20 | PMIDI | power_out | Reverse blocking MOSFET and high side MOSFET connection point for high power IN input; bypass to GND with at least 4.7μF ceramic capacitor. |
| 21 | IN | power_in | Input power supply from AC adapter or alternate power source; bypass to PGND with at least 1μF ceramic capacitor; 10.5V OVP rated. |
| 22 | USB | power_in | USB input power supply from port or AC adapter; bypass to PGND with at least 1μF ceramic capacitor; 6.5V OVP rated. |
| 23 | PMIDU | power_out | Reverse blocking MOSFET and high side MOSFET connection point for USB input; bypass to GND with at least 4.7μF ceramic capacitor. |
| 24 | CE | input | Charge enable input; low logic level enables charging and high logic level disables charging; SYS regulated but BAT disconnected when disabled. |
| 25 | EP | passive | Exposed pad (from the footprint; not named in the datasheet pin table). |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Texas Instruments |
| Package | VQFN-24-EP(4x4) |
| Category | Power Management (PMIC) |
| Pins | 25 |
CAD (KiCad official)
- Symbol:
BQ24166RGET - Footprint:
Package_DFN_QFN:QFN-24-1EP_4x4mm_P0.5mm_EP2.6x2.6mm - 3D model: VQFN-24-EP(4x4) (KiCad packages3D, STEP)
- 3D model files:
bq24166rget-etched.step/bq24166rget-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);bq24166rget.step/bq24166rget.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: Texas Instruments datasheet (39 pp, sha256
4dfca4e8d4de97f8, retrieved 2026-10-07, tier: lcsc) - Datasheet language: Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
- Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-haiku-4-5-20251001(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).