component
BQ24166RGER
Public Made by Adomby adom
Texas Instruments Battery Management, VQFN-24(4x4). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
3D Model
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Symbol & Footprint
Schematic Symbol
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PCB Footprint
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Datasheet
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README
markdownBQ24166RGER
Texas Instruments · Battery Management · VQFN-24(4x4)
BQ24166RGER from Texas Instruments, in a VQFN-24(4x4). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | VDPM | input | Input Voltage DPM programming input; connect resistor divider from IN to GND with VDPM at center tap to set VIN-DPM threshold for dynamic power management. |
| 2 | IUSB3 | input | USB Input Current Limit programming input pin 3; IUSB1/2/3 collectively program USB input current limit for USB2.0/3.0 standards with no effect on IN input. |
| 3 | IUSB2 | input | USB Input Current Limit programming input pin 2; IUSB1/2/3 collectively program USB input current limit for USB2.0/3.0 standards with no effect on IN input. |
| 4 | IUSB1 | input | USB Input Current Limit programming input pin 1; IUSB1/2/3 collectively program USB input current limit for USB2.0/3.0 standards with no effect on IN input. |
| 5 | ISET | input | Charge current programming input; connect resistor from ISET to GND to program fast charge current from 550mA to 2.5A. |
| 6 | DRV | output | Gate drive supply output providing bias for internal MOSFET gate drivers; bypass to PGND with 1μF ceramic capacitor, may drive external loads up to 10mA when supply sufficient. |
| 7 | PG | tri_state | Power Good open-drain output; pulled low when valid supply (between VBAT+VSLP and VOVP) connected to USB or IN, high-impedance otherwise. |
| 8 | CHG | tri_state | Charge Status open-drain output; pulled low at charge cycle start and remains low while charging, high-impedance when charging terminates or no supply connected. |
| 9 | TS | input | Battery NTC thermistor monitor input; connect to center tap of resistor divider from DRV to GND with thermistor to GND providing Hot/Cold temperature shutdown thresholds. |
| 10 | BGATE | output | External P-Channel MOSFET gate driver output connected to external FET gate for low-resistance battery discharge path; low during high-impedance mode and when no input connected. |
| 11 | BAT | bidirectional | Battery positive terminal connection; bypass to GND with minimum 1μF capacitor to support high current transients and minimize parasitic inductance. |
| 12 | BAT | bidirectional | Battery positive terminal connection; bypass to GND with minimum 1μF capacitor to support high current transients and minimize parasitic inductance. |
| 13 | SYS | input | System voltage sense connected to output bulk capacitors; bypass locally with minimum 10μF (47μF recommended for best transient response). |
| 14 | SYS | input | System voltage sense connected to output bulk capacitors; bypass locally with minimum 10μF (47μF recommended for best transient response). |
| 15 | ILIM | input | Input current limit programming input for IN; connect resistor from ILIM to GND to set current limit from 1A to 2.5A with no effect on USB input. |
| 16 | PGND | power_in | Ground terminal connected to thermal pad and circuit ground plane; primary return path for all IC currents. |
| 17 | PGND | power_in | Ground terminal connected to circuit ground plane; return path for all IC currents. |
| 18 | SW | output | Inductor connection output; connect to switched side of external inductor with current returning to PGND through internal low-side MOSFET. |
| 19 | BOOT | output | Bootstrap capacitor connection for high-side MOSFET gate drive; connect 0.01μF ceramic capacitor (>10V rating) from BOOT to SW. |
| 20 | PMIDI | output | High Power input path node connecting reverse blocking and high-side MOSFETs; bypass to GND with 4.7μF ceramic capacitor; not current limited so short-circuit protection required. |
| 21 | IN | power_in | AC Adapter or alternate power supply input rated for 20V with overvoltage protection; bypass to PGND with minimum 1μF ceramic capacitor; 0-2.5A maximum input current. |
| 22 | USB | power_in | USB input power supply rated for 6.5V with overvoltage protection; bypass to PGND with minimum 1μF ceramic capacitor; 0-1.5A maximum input current. |
| 23 | PMIDU | output | USB input path node connecting reverse blocking and high-side MOSFETs; bypass to GND with 4.7μF ceramic capacitor; not current limited so short-circuit protection required. |
| 24 | CE | input | Charge Enable input; logic 0 enables charging and logic 1 disables charging; when disabled SYS remains regulated but BAT disconnects from SYS. |
| 25 | EP | passive | Exposed pad (from the footprint; not named in the datasheet pin table). |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Texas Instruments |
| Package | VQFN-24(4x4) |
| Category | Power Management (PMIC) |
| Pins | 25 |
CAD (KiCad official)
- Symbol:
BQ24166RGER - Footprint:
Package_DFN_QFN:QFN-24-1EP_4x4mm_P0.5mm_EP2.6x2.6mm - 3D model: VQFN-24(4x4) (KiCad packages3D, STEP)
- 3D model files:
bq24166rger-etched.step/bq24166rger-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);bq24166rger.step/bq24166rger.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: Texas Instruments datasheet (39 pp, sha256
4dfca4e8d4de97f8, retrieved 2026-10-01, tier: lcsc) - Datasheet language: Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
- Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-haiku-4-5-20251001(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).