BQ24165RGER from Texas Instruments, in a VQFN-24-EP(4x4). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin	Name	Type	Function
1	VDPM	input	Input DPM programming input; a resistor divider from IN to GND with the center tap connected to VDPM sets the VIN-DPM threshold.
2	IUSB3	input	USB input current limit programming input for the USB3.0 standard; it has no effect on the IN input.
3	IUSB2	input	USB input current limit programming input for the USB2.0 standard; it has no effect on the IN input.
4	IUSB1	input	USB input current limit programming input whose settings are given in Table 1; it has no effect on the IN input.
5	ISET	input	Charge current programming input; a resistor from ISET to GND programs the fast charge current from 550mA to 2.5A.
6	DRV	output	Gate drive supply bypassed to PGND with a 1μF ceramic capacitor; it may drive external loads up to 10mA and is active when the input is connected and VSUPPLY > VUVLO.
7	PG	output	Power good open-drain output pulled low when a valid supply on USB or IN is between VBAT+VSLP and VOVP, and high impedance otherwise.
8	CHG	output	Charge status open-drain output pulled low when a charge cycle starts and while charging, high impedance when charging terminates or no supply exists.
9	CE2	input	JEITA compliance input that reduces the charge voltage by 140mV or halves the charge current per Table 2 when used with CE1.
10	BGATE	output	Drives the gate of an optional external P-channel MOSFET for a low-resistance discharge path, held low in high-impedance mode and when no input is connected.
11	BAT	bidirectional	Battery connection to the positive battery terminal, to be bypassed to GND with at least a 1μF capacitor.
12	BAT	bidirectional	Battery connection to the positive battery terminal, to be bypassed to GND with at least a 1μF capacitor.
13	SYS	input	System voltage sense and charger FET connection, to be bypassed locally with at least 10μF, with 47μF recommended for best transient response.
14	SYS	input	System voltage sense and charger FET connection, to be bypassed locally with at least 10μF, with 47μF recommended for best transient response.
15	ILIM	input	IN input current limit programming input; a resistor from ILIM to GND programs the input current limit from 1A to 2.5A.
16	PGND	power_in	Ground terminal to be connected to the thermal pad and the ground plane of the circuit.
17	PGND	power_in	Ground terminal to be connected to the thermal pad and the ground plane of the circuit.
18	SW	bidirectional	Inductor connection to the switched side of the external inductor.
19	BOOT	input	High-side MOSFET gate driver supply; connect a 0.01μF ceramic capacitor with voltage rating above 10V from BOOT to SW.
20	PMIDI	output	Reverse blocking and high-side MOSFET connection point for the high power input, bypassed to GND with at least 4.7μF; the output is not current limited and any short will damage the IC.
21	IN	input	Input power supply connected to the external DC supply, bypassed to PGND with at least a 1μF ceramic capacitor.
22	USB	input	USB input power supply connected to the external DC supply or USB port, bypassed to PGND with at least a 1μF ceramic capacitor.
23	PMIDU	output	Reverse blocking and high-side MOSFET connection point for the USB input, bypassed to GND with at least 4.7μF; the output is not current limited and any short will damage the IC.
24	CE1	input	JEITA compliance input used with CE2 to change battery regulation and charge current per the JEITA standard, as given in Table 2.
25	EP	passive	Exposed pad (from the footprint; not named in the datasheet pin table).

Key specifications

Parameter	Value
Manufacturer	Texas Instruments
Package	VQFN-24-EP(4x4)
Category	Power Management (PMIC)
Pins	25

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter	Symbol	Min	Typ	Max	Unit	Conditions	Page
Supply current for control, PWM switching	ISUPPLY			15	mA	VUVLO < VSUPPLY < VOVP and VSUPPLY > VBAT+VSLP, PWM switching	4
Leakage current from BAT to the supply	IBATLEAK			5	μA	0°C < TJ < 85°C, VBAT = 4.2 V, VUSB = VIN = 0 V	4
System regulation voltage	VSYS(REG)	3.6	3.7	3.82	V	VBAT < VMINSYS	4
System regulation voltage, battery FET off	VSYSREGFETOFF	4.26	4.33	4.37	V	Battery FET turned off, Charge disable or termination	4
Minimum system regulation voltage	VMINSYS	3.4	3.5	3.62	V	VBAT < VMINSYS, Input current limit or VINDPM active	4
Battery range for BGATE operation		2.5		4.5	V		4
Internal battery charger MOSFET on-resistance, RGE pkg	RON(BAT-SYS)		50	70	mΩ	Measured from BAT to SYS, VBAT = 4.2 V, RGE pkg	4
Battery regulation voltage	VBATREG	4.179	4.2	4.221	V	TA = 25°C, CE1 = CE2 = 0	4
Battery regulation voltage	VBATREG	4.16	4.2	4.24	V	CE1=CE2 = 0 or VWARM < VTS < VCOOL	4
Battery regulation voltage	VBATREG	4.04	4.06	4.08	V	TA = 25°C, CE1=1, CE2=0	4
Battery regulation voltage	VBATREG	4.02	4.06	4.1	V	CE1=1, CE2=0 or VHOT < VTS < VWARM	4
Charge current programmable range	ICHARGE	550		2500	mA		4
Programmable fast charge current factor	KISET	450	490	540	AΩ	TA = 0°C to 125°C, CE1=CE2=0 or VWARM < VTS < VCOOL	4
Programmable fast charge current factor	KISET	225	245	270	AΩ	TA = 0°C to 125°C, CE1 = 1, CE2 = 0 or VCOLD < VTS < VCOOL	4
Battery short threshold	VBATSHRT	2.9	3	3.1	V	VBAT Rising	4
Termination charge current	ITERM	7	10	11.5	%ICHARGE	ICHARGE ≤ 1 A	4
Termination charge current	ITERM	8	10	11	%ICHARGE	ICHARGE >1 A	4
Input current limiting threshold, USB100	IIN_USB	90	95	100	mA	IINUSB=USB100; USB charge mode, VUSB = 5V, current pulled from PMIDU	4
Input current limiting threshold, USB150	IIN_USB	135	142.5	150	mA	IINUSB=USB150; USB charge mode, VUSB = 5V, current pulled from PMIDU	4
Input current limiting threshold, USB500	IIN_USB	450	475	500	mA	IINUSB=USB500; USB charge mode, VUSB = 5V, current pulled from PMIDU	4
Input current limiting threshold, USB800	IIN_USB	700	750	800	mA	IINUSB=USB800; USB charge mode, VUSB = 5V, current pulled from PMIDU	4
Input current limiting threshold, USB900	IIN_USB	800	850	900	mA	IINUSB=USB900; USB charge mode, VUSB = 5V, current pulled from PMIDU	4
Input current limiting threshold, 1.5A	IIN_USB	1250	1400	1500	mA	IINUSB=1.5A; USB charge mode, VUSB = 5V, current pulled from PMIDU	4
Maximum input current limit programmable range for IN input	IINLIM	1000		2500	mA		5
Maximum input current factor for IN input	KILIM	238	251	264	AΩ		5
VDPM threshold	VDPM	1.18	1.2	1.22	V		5
VIN_DPM threshold for USB Input, USB100/USB150	VIN_DPM_USB	4.175	4.28	4.36	V	USB100, USB150	5
VIN_DPM threshold for USB Input, USB500/USB800/USB900/1.5A	VIN_DPM_USB	4.35	4.44	4.52	V	USB500, USB800, USB900, 1.5A current limit selected	5
Internal bias regulator voltage	VDRV	5	5.2	5.45	V	VSUPPLY > 5.45V	5
Under-voltage lockout threshold voltage	VUVLO	3.6	3.8	4	V	VIN or VUSB rising, 150mV Hysteresis	5
Sleep-mode entry threshold	VSUPPLY-VSLP	0	40	100	mV	2.0 V ≤ VBAT ≤ VOREG, VIN falling	5
Input supply OVP threshold voltage, USB	VOVP	6.3	6.5	6.7	V	USB, VUSB Rising	5
Input supply OVP threshold voltage, IN	VOVP	10.3	10.5	10.7	V	IN, VIN Rising	5
Cycle by cycle current limit	ILIMIT	4.1	4.9	5.6	A		5
Safety timer		324	360	396	min		5
Internal top reverse blocking MOSFET on-resistance, USB			95	175	mΩ	IIN_LIMIT = 500 mA, measured from VUSB to PMIDU	5
Internal top reverse blocking MOSFET on-resistance, IN			45	80	mΩ	IIN_LIMIT = 500 mA, measured from VIN to PMIDI	5
Internal top N-channel switching MOSFET on-resistance, PMIDU to SW			100	175	mΩ	Measured from PMIDU to SW	5
Internal top N-channel switching MOSFET on-resistance, PMIDI to SW			65	110	mΩ	Measured from PMIDI to SW	5
Internal bottom N-channel MOSFET on-resistance			65	115	mΩ	Measured from SW to PGND	5
Oscillator frequency	fOSC	1.35	1.5	1.65	MHz		5
TS disable threshold	TSOFF	70		73	%VDRV	VTS rising, 2%VDRV Hysteresis	5
Input voltage range, IN	VIN	4.2		18	V	IN voltage range (footnote 1)	3
IN operating voltage range		4.2		10	V		3
USB voltage range	VUSB	4.2		18	V	USB voltage range (footnote 1)	3
USB operating range		4.2		6	V		3
Input current, IN input	IIN			2.5	A		3
Input current, USB input	IUSB			1.5	A		3
Output current from SW, DC	ISYS			3	A		3
Charging current	IBAT			2.5	A	Charging	3
Operating junction temperature range	TJ	0		125	°C		3
Pin voltage range, IN and USB		-2		20	V	With respect to PGND	3
Pin voltage range, PMIDI, PMIDU, BOOT		-0.3		20	V	With respect to PGND	3
Pin voltage range, SW		-0.7		12	V	With respect to PGND	3
Output current (continuous), SYS and BAT				3.5	A		3
Input current (continuous), IN				2.75	A		3
Input current (continuous), USB				1.75	A		3
Operating free-air temperature range		-40		85	°C		3
Junction temperature	TJ	-40		125	°C		3
Junction-to-ambient thermal resistance, RGE 24 pins	θJA		32.6		°C/W	RGE 24 pins	3

CAD (KiCad official)

Symbol: BQ24165RGER
Footprint: Package_DFN_QFN:QFN-24-1EP_4x4mm_P0.5mm_EP2.6x2.6mm
3D model: VQFN-24-EP(4x4) (KiCad packages3D, STEP)
3D model files: bq24165rger-etched.step / bq24165rger-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); bq24165rger.step / bq24165rger.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

Datasheet: Texas Instruments datasheet (39 pp, sha256 9435ba6f350cac8b, retrieved 2026-11-05, tier: manufacturer)
Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF

BQ24165RGER

Verified BQ24165RGER

Verification log 1 record

3D Model

Symbol & Footprint

Schematic Symbol

PCB Footprint

Datasheet

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