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BQ24161RGER

Texas Instruments · Battery Management ICs · VQFN-24-EP(4x4)

BQ24161RGER from Texas Instruments, in a VQFN-24-EP(4x4). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 N.C. unconnected No connect on the BQ24161 (D- is only used on BQ24160/BQ24163 at this location).
2 PSEL input USB source detection input: high starts USB at 100 mA (BQ24161/8) or 500 mA (BQ24161B), low starts USB at 1.5 A; has no effect on IN and must not be left unconnected.
3 SCL input I2C interface clock; connect to the logic rail through a 10-kΩ resistor.
4 SDA bidirectional I2C interface data; connect to the logic rail through a 10-kΩ resistor.
5 PGND power_in Ground terminal; connect to the thermal pad and the ground plane of the circuit, and it must be grounded at all times.
6 DRV power_out Gate drive supply for the internal MOSFETs; bypass to PGND with a 1-μF ceramic capacitor, and it can drive external loads up to 10 mA.
7 INT output Open-drain status output that pulls low during charging and sends a 128-μs pulse on faults; connect to a logic rail through a 100-kΩ resistor.
8 STAT output Open-drain status output that pulls low during charging and sends a 128-μs pulse on faults; pull up through an LED or a 10-kΩ resistor.
9 TS input Battery pack NTC monitor input connected to the center tap of a resistor divider from DRV to GND, with 4 JEITA thresholds on BQ24161B only; connect to DRV to disable.
10 BGATE output Gate drive for an external P-channel discharge MOSFET; low during high impedance mode and when no input is connected.
11 BAT bidirectional Battery connection to the positive battery terminal; bypass to GND with at least a 1-μF capacitor.
12 BAT bidirectional Battery connection to the positive battery terminal; bypass to GND with at least a 1-μF capacitor.
13 SYS power_out System voltage sense and charger FET connection; connect at the output bulk capacitors and bypass with at least 10 μF (47 μF recommended).
14 SYS power_out System voltage sense and charger FET connection; connect at the output bulk capacitors and bypass with at least 10 μF (47 μF recommended).
15 PGND power_in Ground terminal; connect to the thermal pad and the ground plane of the circuit, and it must be grounded at all times.
16 PGND power_in Ground terminal; connect to the thermal pad and the ground plane of the circuit, and it must be grounded at all times.
17 PGND power_in Ground terminal; connect to the thermal pad and the ground plane of the circuit, and it must be grounded at all times.
18 SW output Inductor connection; connect to the switched side of the external inductor.
19 BOOT input High-side MOSFET gate driver supply; connect a 0.01-μF ceramic capacitor (rated above 10 V) from BOOT to SW.
20 PMIDI power_out Reverse blocking and high-side MOSFET connection point for the high-power IN input; bypass with at least 4.7 μF, and the output is not current limited.
21 IN power_in Input power supply from the external DC supply (rated 20 V absolute max, 4.2 V to 10 V operating for BQ24161); bypass to PGND with at least 1 μF.
22 USB power_in USB input power supply from an AC adapter or USB port (4.2 V to 6 V operating); bypass to PGND with at least 1 μF.
23 PMIDU power_out Reverse blocking and high-side MOSFET connection point for the USB input; bypass with at least 4.7 μF, and the output is not current limited.
24 CD input Hardware chip disable input: high places the device in high-z mode, low is normal operation; do not leave unconnected.
25 EP passive Exposed pad (from the footprint; not named in the datasheet pin table).

Key specifications

Parameter Value
Manufacturer Texas Instruments
Package VQFN-24-EP(4x4)
Category Power Supply Chip
Pins 25

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
System regulation voltage, charge enabled, VBAT < VMINSYS VSYS(REG) 3.6 3.7 3.82 V Charge Enabled, VBAT < VMINSYS, BQ24160, 1, 1B, 8 8
System regulation voltage, battery FET off VSYS(REG) 1.5 3 4.17 % above VBATREG Battery FET turned off (Charge Disabled, TS Fault or Charging Terminated); VBATREG + x% 8
Minimum system regulation voltage VMINSYS 3.4 3.5 3.62 V Charge enabled, VBAT < VMINSYS, Input current limit or VINDPM active, BQ24160, 1, 1B, 8 8
Battery charger MOSFET on-resistance RON(BAT-SYS) 50 70 mΩ Measured from BAT to SYS, VBAT = 4.2V, RGE pkg 8
Charge voltage programmable range VBATREG 3.5 4.44 V Operating in voltage regulation, Programmable range 8
Voltage regulation accuracy VBATREG -1 1 % Operating in voltage regulation 8
Fast charge current range ICHARGE 550 2500 mA VBATSHRT ≤ VBAT < VBAT(REG) programmable range 8
Fast charge current accuracy ICHARGE -10 10 % 0°C to 125°C 8
Battery short circuit threshold VBATSHRT 1.9 2 2.1 V 100mV Hysteresis, BQ24161, 3, 8 8
Termination charge current accuracy ITERM -40 40 % ITERM = 50mA 8
Termination charge current accuracy ITERM -20 20 % ITERM = 100mA 8
Termination charge current accuracy ITERM -15 15 % ITERM ≥ 150mA 8
USB input current limit IIN_USB 90 95 100 mA USB charge mode, VUSB = 5V, IUSBLIM = USB100 9
USB input current limit IIN_USB 450 475 500 mA USB charge mode, VUSB = 5V, IUSBLIM = USB500 9
USB input current limit IIN_USB 1250 1400 1500 mA USB charge mode, VUSB = 5V, IUSBLIM = 1.5A 9
IN input current limit IIN_IN 1.35 1.5 1.65 A IN charge mode, VIN = 5V, IINLIM = 1.5A 9
IN input current limit IIN_IN 2.3 2.5 2.8 A IN charge mode, VIN = 5V, IINLIM = 2.5A 9
Input based DPM threshold range VIN_DPM 4.2 4.76 V Charge mode, programmable via I2C, both inputs 9
VIN_DPM threshold accuracy VIN_DPM -2 2 % 9
Internal bias regulator voltage VDRV 5 5.2 5.45 V VSUPPLY > 5.45V 9
IC active threshold voltage VUVLO 3.6 3.8 4 V VIN rising 9
Sleep-mode entry threshold VSLP 0 40 100 mV 2.0V ≤VBAT ≤VBATREG, VIN falling 9
Sleep-mode exit hysteresis VSLP_EXIT 40 100 175 mV 2.0V ≤VBAT ≤VBATREG 9
USB input supply OVP threshold VOVP 6.3 6.5 6.7 V USB, VUSB Rising 9
IN input supply OVP threshold VOVP 10.3 10.5 10.7 V IN, VIN Rising (BQ24160/1/1B/3) 9
Battery OVP threshold voltage VBOVP 1.025 1.05 1.075 V VBAT threshold over VOREG to turn off charger during charge; × VBATREG 9
Cycle-by-cycle current limit ILIMIT 4.1 4.9 5.6 A VSYS shorted 9
Safety timer accuracy -20 20 % BQ24160/1/1B/3 Only 10
Reverse blocking MOSFET on-resistance (USB to PMIDU) 95 175 mΩ IIN_LIMIT = 500mA, Measured from USB to PMIDU 10
Reverse blocking MOSFET on-resistance (IN to PMIDI) 45 80 mΩ IIN_LIMIT = 500mA, Measured from IN to PMIDI 10
Top switching MOSFET on-resistance (PMIDU to SW) 100 175 mΩ Measured from PMIDU to SW 10
Top switching MOSFET on-resistance (PMIDI to SW) 65 110 mΩ Measured from PMIDI to SW 10
Bottom N-channel MOSFET on-resistance 65 115 mΩ Measured from SW to PGND 10
Oscillator frequency fOSC 1.35 1.5 1.65 MHz 10
Good Battery threshold VBATGD 3.6 3.8 3.9 V 10
PSEL, CD input high logic level VIH 1.3 V 9
PSEL, CD input low logic level VIL 0.4 V 9
Low-level output saturation voltage (STAT, INT) VOL 0.4 V IO = 10mA, sink current 9
Supply current, PWM switching ISUPPLY 15 mA PWM switching 8
Supply current, High-Z Mode ISUPPLY 175 μA 0°C < TJ < 85°C, High-Z Mode 8
Pin voltage IN, USB -2 20 V with respect to VSS 7
Pin voltage PMIDI, PMIDU, BOOT -0.3 20 V with respect to VSS 7
Pin voltage SW -0.7 12 V with respect to VSS 7
Pin voltage SDA, SCL, SYS, BAT, STAT, BGATE, DRV, TS, D+, D-, INT, PSEL, CD -0.3 7 V with respect to VSS 7
BOOT to SW voltage -0.3 7 V 7
Junction temperature TJ -40 125 °C 7
Storage temperature range Tstg -65 150 °C 7
Operating free-air temperature range -40 85 °C 7
IN operating voltage range (BQ24160/1/3) VIN 4.2 10 V 7
USB operating range VUSB 4.2 6 V 7
Operating junction temperature range TJ 0 125 °C 7
Junction-to-ambient thermal resistance θJA 32.6 °C/W 24 PINS (RGE) 8
Junction-to-case (top) thermal resistance θJCtop 30.5 °C/W 24 PINS (RGE) 8

CAD (KiCad official)

  • Symbol: BQ24161RGER
  • Footprint: Package_DFN_QFN:QFN-24-1EP_4x4mm_P0.5mm_EP2.6x2.6mm
  • 3D model: VQFN-24-EP(4x4) (KiCad packages3D, STEP)
  • 3D model files: bq24161rger-etched.step / bq24161rger-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); bq24161rger.step / bq24161rger.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Texas Instruments datasheet (54 pp, sha256 5c151470748871c8, retrieved 2026-11-02, tier: manufacturer)
  • Datasheet language: Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-sonnet-5-5 (text), consensus claude-opus-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF