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BLUENRG-345AC

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STMicroelectronics Microcontrollers (MCU/MPU/SOC), TQFN-32-EP(5x5). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

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BLUENRG-345AC

STMicroelectronics · Microcontrollers (MCU/MPU/SOC) · TQFN-32-EP(5x5)

BLUENRG-345AC from STMicroelectronics, in a TQFN-32-EP(5x5). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 PB3 bidirectional 5 V tolerant I/O (FT_a) with wakeup and ADC_VINP0 analog input; alternate functions USART_CTS, LPUART_TX, TIM1_CH4.
2 PB2 bidirectional 5 V tolerant I/O (FT_a) with wakeup and ADC_VINM0 analog input; alternate functions USART_RTS_DE, PDM_DATA, TIM1_CH3.
3 PB1 bidirectional 5 V tolerant I/O (FT_a) with wakeup and ADC_VINP1 analog input; alternate functions SPI1_NSS, PDM_CLK, TIM1_ETR.
4 PB0 bidirectional 5 V tolerant I/O (FT_a) with wakeup and ADC_VINM1 analog input; alternate functions USART_RX, LPUART_RTS_DE, TIM1_CH2N.
5 PA11 bidirectional 5 V tolerant I/O (FT) with wakeup, GPIO in DEEPSTOP and RTC_OUT additional function; alternate functions MCO, SPI1_NSS, RX_SEQUENCE, SPI3_MOSI, TIM1_CH6, I2S3_SD.
6 PA10 bidirectional 5 V tolerant I/O (FT) with BOOT, wakeup and GPIO in DEEPSTOP functions, LCO additional function; alternate functions SPI1_MISO, TX_SEQUENCE, SPI3_MCK, TIM1_CH5, I2S3_MCK.
7 PA9 bidirectional 5 V tolerant I/O (FT) with wakeup and GPIO in DEEPSTOP, LCO additional function; alternate functions USART_TX, SPI1_SCK, RTC_OUT, SPI3_NSS, TIM1_CH4, I2S3_WS.
8 PA8 bidirectional 5 V tolerant I/O (FT) with wakeup and GPIO in DEEPSTOP, RTC_OUT additional function; alternate functions USART_RX, SPI1_MOSI, RX_SEQUENCE, SPI3_MISO, TIM1_CH3, I2S3_MISO.
9 PA0 bidirectional I/O (FT_f, Fm+ capable, 5 V tolerant) with wakeup; alternate functions I2C1_SCL, USART_CTS, SPI2_MCK, TIM1_CH3, I2S2_MCK.
10 PA1 bidirectional I/O (FT_f, Fm+ capable, 5 V tolerant) with wakeup; alternate functions I2C1_SDA, SPI2_MISO, USART_TX, TIM1_CH4, I2S2_MISO.
11 PA2 bidirectional 5 V tolerant I/O (FT) with wakeup; SWDIO debug function listed on this pin, alternate functions USART_CK, TIM_BKIN, SPI3_MCK, TIM1_CH5, I2S3_MCK.
12 PA3 bidirectional 5 V tolerant I/O (FT) with wakeup; SWCLK debug function listed on this pin, alternate functions USART_RTS_DE, TIM_BKIN2, SPI3_SCK, TIM1_CH6, I2S3_SCK.
13 VDD2 power_in Battery voltage input, 1.7 to 3.6 V.
14 RF1 bidirectional RF input/output with 50 Ω impedance.
15 VDDRF power_in Battery voltage input, 1.7 to 3.6 V.
16 OSCOUT passive 32 MHz crystal connection (RF I/O pin).
17 OSCIN passive 32 MHz crystal connection (RF I/O pin).
18 PB15 bidirectional 5 V tolerant I/O (FT); alternate functions I2C1_SMBA, TX_SEQUENCE, MCO, TIM1_CH4N, TIM1_CH6, USART_TX.
19 PB14 bidirectional 5 V tolerant I/O (FT_a) with VIN_PVD additional function; alternate functions SPI1_MOSI, I2C2_SDA, TIM1_ETR, TIM1_CH3N, TIM1_CH5, USART_RX.
20 PB13 bidirectional 5 V tolerant I/O (FT) with SXTAL1 additional function; alternate functions SPI1_MISO, I2C2_SCL, PDM_CLK, TIM1_BKIN2, TIM1_CH4.
21 PB12 bidirectional 5 V tolerant I/O (FT) with SXTAL0 additional function; alternate functions SPI1_SCK, LCO, PDM_DATA, TIM1_BKIN, TIM1_CH3.
22 VFBSD power_out SMPS output.
23 VSSSD power_in SMPS ground.
24 VLXSD bidirectional SMPS input/output.
25 VDDSD power_in Battery voltage input, 1.7 to 3.6 V.
26 RSTN bidirectional Reset pin (RST type) with weak pull-up resistor.
27 VCAP power_out 1.2 V digital core supply pin.
28 PB7 bidirectional 5 V tolerant I/O (FT_f, Fm+ capable) with wakeup; alternate functions I2C2_SDA, SPI2_SCK, LPUART_RX, TIM1_CH2, I2S2_SCK.
29 PB6 bidirectional 5 V tolerant I/O (FT_f, Fm+ capable) with wakeup; alternate functions I2C2_SCL, SPI2_NSS, LPUART_TX, TIM1_CH1, I2S2_WS.
30 PB5 bidirectional 3.6 V tolerant I/O (TT, not 5 V tolerant per note 1) with wakeup and PGA_VBIAS_MIC additional function; alternate functions LPUART_RX, SPI2_MOSI, PDM_CLK, I2S2_SD.
31 PB4 bidirectional 5 V tolerant I/O (FT) with wakeup and PGA_VIN additional function; alternate functions LPUART_TX, SPI2_MISO, PDM_DATA, I2S2_MISO.
32 VDD1 power_in Battery voltage input, 1.7 to 3.6 V.
33 EP passive Exposed pad (from the footprint; not named in the datasheet pin table).

Key specifications

Parameter Value
Manufacturer STMicroelectronics
Package TQFN-32-EP(5x5)
Category Embedded Processors & Controllers
Pins 33

CAD (KiCad official)

  • Symbol: BLUENRG-345AC
  • Footprint: Package_DFN_QFN:QFN-32-1EP_5x5mm_P0.5mm_EP3.3x3.3mm
  • 3D model: TQFN-32-EP(5x5) (KiCad packages3D, STEP)
  • 3D model files: bluenrg-345ac-etched.step / bluenrg-345ac-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); bluenrg-345ac.step / bluenrg-345ac.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: STMicroelectronics datasheet (73 pp, sha256 614fe4d1991b0774, retrieved 2026-10-08, tier: lcsc)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF