component
BL9161G-12BARN
Public Made by Adomby adom
BL Shanghai Belling Voltage Regulators - Linear, Low Drop Out (LDO) Regulators, SOT-23-5. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
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BL9161G-12BARN
BL Shanghai Belling · Voltage Regulators - Linear, Low Drop Out (LDO) Regulators · SOT-23-5
BL9161G-12BARN from BL Shanghai Belling, in a SOT-23-5. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | VIN | power_in | Power input voltage; the datasheet gives an operating range of 2.2V to 6V and an absolute maximum of -0.3V to +6V. |
| 2 | GND | power_in | Ground reference pin; the datasheet asks that the PCB use a separate ground plane for VIN and VOUT, connected only at the GND pin. |
| 3 | EN | input | Chip enable with an internal pull-down resistor; the LDO turns on when EN is above 1.2V (VIH) and shuts down below 0.4V (VIL), and the EN pin voltage is limited to -0.3V to VIN. |
| 4 | NC | unconnected | No connection. |
| 5 | VOUT | power_out | Regulated output voltage; the output current is limited to 300mA and the output voltage pin is rated -0.3V to VIN+0.3V. |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | BL Shanghai Belling |
| Package | SOT-23-5 |
| Category | Power Management (PMIC) |
| Pins | 5 |
Electrical characteristics
Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Input Voltage | VIN | 2.2 | 6 | V | 4 | ||
| Output Voltage Accuracy | VOUT | -2 | 2 | % | VIN=Vout+1V, IOUT=1mA | 4 | |
| Current Limit | ILIM | 360 | 450 | mA | RLOAD=1 | 4 | |
| Quiescent Current | IQ | 70 | 110 | µA | VEN>1.2V, IOUT=0mA | 4 | |
| Dropout Voltage | VDROP | 135 | 200 | mV | IOUT=200mA, VOUT=3.3V | 4 | |
| Dropout Voltage | VDROP | 205 | 300 | mV | IOUT=300mA, VOUT=3.3V | 4 | |
| Line Regulation | ΔVLINE | 0.02 | 0.17 | %/V | VIN=Vout+1V to 5.5V, IOUT=1mA | 4 | |
| Output Voltage Temperature Coefficient | TCVOUT | -60 | 60 | ppm/℃ | IOUT=1mA | 4 | |
| Standby Current | ISTBY | 0.01 | 1 | µA | VEN=GND, Shutdown | 4 | |
| EN Input Threshold Logic Low | VIL | 0.4 | V | VIN=3V to 5.5V, Shutdown | 4 | ||
| EN Input Threshold Logic High | VIH | 1.2 | V | VIN=3V to 5.5V, Start up | 4 | ||
| Load Regulation | ΔVLOAD | 20 | mV | 1mA<IOUT<300mA | 4 | ||
| EN Input Bias Current | IIBSD | 2 | µA | VEN=GND or VIN | 4 | ||
| Output Noise Voltage | eNO | 180 | VRMS | 10Hz to100KHz, IOUT=100mA | 4 | ||
| Power Supply Rejection Ratio | PSRR | -75 | dB | f=217Hz, IOUT=10mA | 4 | ||
| Power Supply Rejection Ratio | PSRR | -71 | dB | f=1KHz, IOUT=10mA | 4 | ||
| Power Supply Rejection Ratio | PSRR | -55 | dB | f=10KHz, IOUT=10mA | 4 | ||
| Thermal Shutdown Temperature | TSD | 170 | ℃ | Shutdown, Temp increasing | 4 | ||
| Thermal Shutdown Hysteresis | TSDHY | 30 | ℃ | 4 | |||
| Input Supply Voltage (absolute maximum) | VIN | -0.3 | 6 | V | 2 | ||
| EN Pin Input Voltage (upper limit VIN) | -0.3 | V | 2 | ||||
| Output Voltages (upper limit VIN+0.3V) | -0.3 | V | 2 | ||||
| Output Current | 300 | mA | 2 | ||||
| Maximum Junction Temperature | 150 | °C | 2 | ||||
| Operating Temperature Range | -40 | 85 | °C | Note 2: guaranteed 0°C to 70°C; -40°C to 85°C assured by design and characterization | 2 | ||
| Storage Temperature Range | -65 | 125 | °C | 2 | |||
| Lead Temperature (Soldering) | 300 | °C | Soldering, 10s | 2 | |||
| Junction-to-Ambient Thermal Resistance (SOT23-5) | ӨJA | 250 | °C/W | 2 | |||
| Junction-to-Case Thermal Resistance (SOT23-5) | ӨJC | 130 | °C/W | 2 |
CAD (KiCad official)
- Symbol:
BL9161G-12BARN - Footprint:
Package_TO_SOT_SMD:SOT-23-5 - 3D model: SOT-23-5 (KiCad packages3D, STEP)
- 3D model files:
bl9161g-12barn-etched.step/bl9161g-12barn-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);bl9161g-12barn.step/bl9161g-12barn.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: BL Shanghai Belling datasheet (12 pp, sha256
74f47540de0b9365, retrieved 2026-10-18, tier: lcsc) - Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-haiku-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).
# BL9161G-12BARN
**BL Shanghai Belling** · Voltage Regulators - Linear, Low Drop Out (LDO) Regulators · SOT-23-5
BL9161G-12BARN from BL Shanghai Belling, in a SOT-23-5. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
## Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | VIN | power_in | Power input voltage; the datasheet gives an operating range of 2.2V to 6V and an absolute maximum of -0.3V to +6V. |
| 2 | GND | power_in | Ground reference pin; the datasheet asks that the PCB use a separate ground plane for VIN and VOUT, connected only at the GND pin. |
| 3 | EN | input | Chip enable with an internal pull-down resistor; the LDO turns on when EN is above 1.2V (VIH) and shuts down below 0.4V (VIL), and the EN pin voltage is limited to -0.3V to VIN. |
| 4 | NC | unconnected | No connection. |
| 5 | VOUT | power_out | Regulated output voltage; the output current is limited to 300mA and the output voltage pin is rated -0.3V to VIN+0.3V. |
## Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | BL Shanghai Belling |
| Package | SOT-23-5 |
| Category | Power Management (PMIC) |
| Pins | 5 |
## Electrical characteristics
Limits as printed in the datasheet (page.json `metadata.characteristics` carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Input Voltage | VIN | 2.2 | | 6 | V | | 4 |
| Output Voltage Accuracy | VOUT | -2 | | 2 | % | VIN=Vout+1V, IOUT=1mA | 4 |
| Current Limit | ILIM | | 360 | 450 | mA | RLOAD=1 | 4 |
| Quiescent Current | IQ | | 70 | 110 | µA | VEN>1.2V, IOUT=0mA | 4 |
| Dropout Voltage | VDROP | | 135 | 200 | mV | IOUT=200mA, VOUT=3.3V | 4 |
| Dropout Voltage | VDROP | | 205 | 300 | mV | IOUT=300mA, VOUT=3.3V | 4 |
| Line Regulation | ΔVLINE | | 0.02 | 0.17 | %/V | VIN=Vout+1V to 5.5V, IOUT=1mA | 4 |
| Output Voltage Temperature Coefficient | TCVOUT | -60 | | 60 | ppm/℃ | IOUT=1mA | 4 |
| Standby Current | ISTBY | | 0.01 | 1 | µA | VEN=GND, Shutdown | 4 |
| EN Input Threshold Logic Low | VIL | | | 0.4 | V | VIN=3V to 5.5V, Shutdown | 4 |
| EN Input Threshold Logic High | VIH | 1.2 | | | V | VIN=3V to 5.5V, Start up | 4 |
| Load Regulation | ΔVLOAD | | 20 | | mV | 1mA<IOUT<300mA | 4 |
| EN Input Bias Current | IIBSD | | 2 | | µA | VEN=GND or VIN | 4 |
| Output Noise Voltage | eNO | | 180 | | VRMS | 10Hz to100KHz, IOUT=100mA | 4 |
| Power Supply Rejection Ratio | PSRR | | -75 | | dB | f=217Hz, IOUT=10mA | 4 |
| Power Supply Rejection Ratio | PSRR | | -71 | | dB | f=1KHz, IOUT=10mA | 4 |
| Power Supply Rejection Ratio | PSRR | | -55 | | dB | f=10KHz, IOUT=10mA | 4 |
| Thermal Shutdown Temperature | TSD | | 170 | | ℃ | Shutdown, Temp increasing | 4 |
| Thermal Shutdown Hysteresis | TSDHY | | 30 | | ℃ | | 4 |
| Input Supply Voltage (absolute maximum) | VIN | -0.3 | | 6 | V | | 2 |
| EN Pin Input Voltage (upper limit VIN) | | -0.3 | | | V | | 2 |
| Output Voltages (upper limit VIN+0.3V) | | -0.3 | | | V | | 2 |
| Output Current | | | | 300 | mA | | 2 |
| Maximum Junction Temperature | | | | 150 | °C | | 2 |
| Operating Temperature Range | | -40 | | 85 | °C | Note 2: guaranteed 0°C to 70°C; -40°C to 85°C assured by design and characterization | 2 |
| Storage Temperature Range | | -65 | | 125 | °C | | 2 |
| Lead Temperature (Soldering) | | | | 300 | °C | Soldering, 10s | 2 |
| Junction-to-Ambient Thermal Resistance (SOT23-5) | ӨJA | | 250 | | °C/W | | 2 |
| Junction-to-Case Thermal Resistance (SOT23-5) | ӨJC | | 130 | | °C/W | | 2 |
## CAD (KiCad official)
- Symbol: `BL9161G-12BARN`
- Footprint: `Package_TO_SOT_SMD:SOT-23-5`
- 3D model: SOT-23-5 (KiCad packages3D, STEP)
- 3D model files: `bl9161g-12barn-etched.step` / `bl9161g-12barn-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `bl9161g-12barn.step` / `bl9161g-12barn.glb` are the bare package body.
## Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- **Datasheet:** [BL Shanghai Belling datasheet](https://jlcpcb.com/api/file/downloadByFileSystemAccessId/8588954728504311808) (12 pp, sha256 `74f47540de0b9365`, retrieved 2026-10-18, tier: lcsc)
- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.3`, primary `claude-haiku-5-5` (text), consensus `claude-sonnet-5-5` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
- **CAD:** KiCad official libraries (CC-BY-SA 4.0).
[Datasheet PDF](docs/bl9161g-12barn-datasheet.pdf)