component

BL7142WL

Public Made by Adom

by adom

BL Shanghai Belling Digital Isolators, SOIC-16-300mil. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

componentsignal isolation devicesbl7142wlfactory-2.0.0extractor-text
Overview Files Discover Packages Releases Dependencies Issues Breadcrumbs Pull Requests Activity
main
bl7142wl / README.md
History Download
Ray Publish 0.1.0 8110f2b 10d ago

BL7142WL

BL Shanghai Belling · Digital Isolators · SOIC-16-300mil

BL7142WL from BL Shanghai Belling, in a SOIC-16-300mil. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 VDD1 power_in Side-1 supply; recommended VDD1 range is 2.35 V to 5.5 V, and the datasheet calls for two external VDD bypass capacitors (100 nF, within 2 mm of the device).
2 GND1 power_in Side-1 reference ground for the side-1 supply and logic.
3 VIA input Channel A forward input on side 1; logic input thresholds are VIH ≥ 0.7×VDDI and VIL ≤ 0.25×VDDI.
4 VIB input Channel B forward input on side 1; logic input thresholds are VIH ≥ 0.7×VDDI and VIL ≤ 0.25×VDDI.
5 VOC output Channel C reverse output on side 1 (BL7142 assignment of the shared VIC/VOC pin); the output is high-impedance when the enable is low.
6 VOD output Channel D reverse output on side 1 (BL7142 assignment of the shared VID/VOD pin); the output is high-impedance when the enable is low.
7 EN1 input Side-1 output enable, active high; if left open the enable defaults to enabled, and a low level puts the side-1 outputs in high impedance.
8 GND1 power_in Side-1 reference ground (second side-1 ground pin).
9 GND2 power_in Side-2 reference ground for the side-2 supply and logic.
10 EN2 input Side-2 output enable, active high; if left open the enable defaults to enabled, and a low level puts the side-2 outputs in high impedance.
11 VID input Channel D forward input on side 2 (BL7142 assignment of the shared VOD/VID pin); logic input thresholds are VIH ≥ 0.7×VDDI and VIL ≤ 0.25×VDDI.
12 VIC input Channel C forward input on side 2 (BL7142 assignment of the shared VOC/VIC pin); logic input thresholds are VIH ≥ 0.7×VDDI and VIL ≤ 0.25×VDDI.
13 VOB output Channel B output on side 2, following input VIB across the isolation barrier; default level set by the L/H suffix when side-1 power or signal is lost.
14 VOA output Channel A output on side 2, following input VIA across the isolation barrier; default level set by the L/H suffix when side-1 power or signal is lost.
15 GND2 power_in Side-2 reference ground (second side-2 ground pin).
16 VDD2 power_in Side-2 supply; recommended VDD2 range is 2.35 V to 5.5 V, with a 100 nF bypass capacitor.

Key specifications

Parameter Value
Manufacturer BL Shanghai Belling
Package SOIC-16-300mil
Category Signal Isolation Devices
Pins 16

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
VDD1, VDD2 supply voltage (recommended) VDD1,VDD2 2.35 5.5 V 3
VDD UVLO rising threshold VDD(UVLO+) 1.75 2 V 3
VDD UVLO falling threshold VDD(UVLO-) 1.55 1.65 V 3
VDD UVLO hysteresis VHYS(UVLO) 10 70 230 mV 3
High-level output current IOH -4 mA VDDO=5V 3
High-level output current IOH -2 mA VDDO=3.3V 3
High-level output current IOH -1 mA VDDO=2.5V 3
Low-level output current IOL 4 mA VDDO=5V 3
Low-level output current IOL 2 mA VDDO=3.3V 3
Low-level output current IOL 1 mA VDDO=2.5V 3
Input threshold logic low (lower limit) VIL 0 V 3
Signal data rate DR 0 100 Mbps 3
Ambient temperature TA -40 25 125 ℃ 3
VDD1, VDD2 supply voltage (absolute) VDD1,VDD2 -0.5 6 V 3
Input/output voltage (lower limit) V -0.5 V 3
Output current IO -20 20 mA 3
Junction temperature TJ 150 ℃ 3
Storage temperature range TSTG -65 150 ℃ 3
ESD human body model VESD -6000 6000 V HBM, ANSI/ESDA/JEDEC JS-001-2017 3
ESD charged device model VESD -1500 1500 V CDM, ANSI/ESDA/JEDEC JS-002-2018 3
ESD machine model VESD -400 400 V MM, JESD22-A115C 3
External clearance CLR 8 mm W (SOIC16 wide body) column 4
External creepage CPG 8 mm W (SOIC16 wide body) column 4
Internal gap (DTI) DTI 18 μm 4
Comparative tracking index CTI 600 V Per DIN IEC UL; printed as >600 4
Maximum repetitive peak isolation voltage VIORM 2121 VPK AC voltage (bipolar); W column 4
Maximum working isolation voltage (AC) VIOWM 1500 VRMS AC voltage; W column 4
Maximum working isolation voltage (DC) VIOWM 2121 VDC DC voltage; W column 4
Maximum transient isolation voltage VIOTM 8000 VPK VTEST=VIOTM, t=60 s 4
Maximum surge isolation voltage VIOSM 8000 VPK 1.2/50 μs waveform, VTEST=1.6×VIOSM 4
Maximum isolation voltage VISO 5 kVRMS VTEST=VISO, t=60 s (certification) 4
Maximum power dissipation (total) PD 260 mW VDD1=VDD2=5.5 V, TJ=150°C, CL=15 pF, 50-MHz 50% duty square-wave input 4
Maximum power dissipation, side 1 PD1 130 mW VDD1=VDD2=5.5 V, TJ=150°C, CL=15 pF, 50-MHz 50% duty square-wave input 4
Maximum power dissipation, side 2 PD2 130 mW VDD1=VDD2=5.5 V, TJ=150°C, CL=15 pF, 50-MHz 50% duty square-wave input 4
Input high-level leakage current IIH 5 μA VIH=VDDI; VDD1=VDD2=5V±10% 5
Input low-level leakage current IIL -10 μA VIL=0V; VDD1=VDD2=5V±10% 5
Output low-level voltage VOL 0.2 0.3 V IOL=4mA; Fig 7-1; VDD1=VDD2=5V±10% 5
Common-mode transient immunity CMTI 80 100 kV/μs Fig 7-2; VDD1=VDD2=5V±10% 5
Output low-level voltage VOL 0.06 0.1 V IOL=2mA; Fig 7-1; VDD1=VDD2=3.3V±10% 5
Output low-level voltage VOL 0.03 0.05 V IOL=1mA; Fig 7-1; VDD1=VDD2=2.5V±10% 5
Propagation delay time tPLH, tPHL 7 11 15 ns Fig 7-1; VDD1=VDD2=5V±10% 9
Pulse width distortion PWD 0.2 3 ns /tPLH-tPHL/; VDD1=VDD2=5V±10% 9
Output skew between chips tsk(pp) 4.5 ns VDD1=VDD2=5V±10% 9
Disable propagation delay, output high to high-Z tPHZ 20 28 ns VDD1=VDD2=5V±10% 9
Disable propagation delay, output low to high-Z tPLZ 18 24 ns VDD1=VDD2=5V±10% 9
Output high-level voltage VOH 4.8 V IOH=-4mA; Fig 7-1; VDD1=VDD2=5V±10% 5
Input threshold hysteresis VI(HYS) 1.24 V VDD1=VDD2=5V±10% 5
Output impedance ZO 43 Ω ZO=VOL/IOL; VDD1=VDD2=5V±10% 5
Output high-level voltage VOH 3.2 V IOH=-2mA; Fig 7-1; VDD1=VDD2=3.3V±10% 5
Input threshold hysteresis VI(HYS) 0.9 V VDD1=VDD2=3.3V±10% 5
Output impedance ZO 30 Ω ZO=VOL/IOL; VDD1=VDD2=3.3V±10% 5
Output high-level voltage VOH 2.45 V IOH=-1mA; Fig 7-1; VDD1=VDD2=2.5V±10% 5
Input threshold hysteresis VI(HYS) 0.85 V VDD1=VDD2=2.5V±10% 5
Output impedance ZO 34 Ω ZO=VOL/IOL; VDD1=VDD2=2.5V±10% 5

CAD (KiCad official)

  • Symbol: BL7142WL
  • Footprint: Package_SO:SOIC-16_3.9x9.9mm_P1.27mm
  • 3D model: SOIC-16-300mil (KiCad packages3D, STEP)
  • 3D model files: bl7142wl-etched.step / bl7142wl-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); bl7142wl.step / bl7142wl.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: BL Shanghai Belling datasheet (16 pp, sha256 92b7c28285aa66e6, retrieved 2026-10-21, tier: lcsc)
  • Datasheet language: Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF