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BL7142WH

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BL Shanghai Belling Digital Isolators, SOIC-16-300mil. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

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BL7142WH

BL Shanghai Belling · Digital Isolators · SOIC-16-300mil

BL7142WH from BL Shanghai Belling, in a SOIC-16-300mil. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 VDD1 power_in Side-1 supply pin; the recommended VDD1 range is 2.35 V to 5.5 V, and the absolute maximum supply is 6 V.
2 GND1 power_in Side-1 reference ground; all side-1 voltages are referenced to GND1.
3 VIA input Channel A input on side 1; logic-high threshold is at least 0.7 x VDDI and logic-low threshold is at most 0.25 x VDDI.
4 VIB input Channel B input on side 1; logic-high threshold is at least 0.7 x VDDI and logic-low threshold is at most 0.25 x VDDI.
5 VOC output Channel C output on side 1 (reverse-direction channel on BL7142); rated IOH -4 mA and IOL 4 mA at VDDO = 5 V, with absolute output current limit of -20 mA to 20 mA.
6 VOD output Channel D output on side 1 (reverse-direction channel on BL7142); rated IOH -4 mA and IOL 4 mA at VDDO = 5 V, with absolute output current limit of -20 mA to 20 mA.
7 EN1 input Side-1 output enable, active high; floating is treated as enabled, and a low level puts side-1 outputs in high impedance.
8 GND1 power_in Side-1 reference ground (second GND1 pin, internally tied to pin 2).
9 GND2 power_in Side-2 reference ground; all side-2 voltages are referenced to GND2.
10 EN2 input Side-2 output enable, active high; floating is treated as enabled, and a low level puts side-2 outputs in high impedance.
11 VID input Channel D input on side 2 (reverse-direction channel on BL7142); logic-high threshold is at least 0.7 x VDDI and logic-low threshold is at most 0.25 x VDDI.
12 VIC input Channel C input on side 2; logic-high threshold is at least 0.7 x VDDI and logic-low threshold is at most 0.25 x VDDI.
13 VOB output Channel B output on side 2; rated IOH -4 mA and IOL 4 mA at VDDO = 5 V, with absolute output current limit of -20 mA to 20 mA.
14 VOA output Channel A output on side 2; rated IOH -4 mA and IOL 4 mA at VDDO = 5 V, with absolute output current limit of -20 mA to 20 mA.
15 GND2 power_in Side-2 reference ground (second GND2 pin, internally tied to pin 9).
16 VDD2 power_in Side-2 supply pin; the recommended VDD2 range is 2.35 V to 5.5 V, and the absolute maximum supply is 6 V.

Key specifications

Parameter Value
Manufacturer BL Shanghai Belling
Package SOIC-16-300mil
Category Signal Isolation Devices
Pins 16

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
电源电压 (绝对最大额定值) VDD1，VDD2 -0.5 6 V 3
输入/输出电压 V -0.5 V 3
输出电流 IO -20 20 mA 3
结温 TJ 150 ℃ 3
存储温度范围 TSTG -65 150 ℃ 3
最大功耗 (BL7142) PD 260 mW VCC1=VCC2=5.5 V, TJ=150°C, CL=15 pF, 输入 50-MHz 50% 占空比方波 4
1侧最大功耗 (BL7142) PD1 130 mW VCC1=VCC2=5.5 V, TJ=150°C, CL=15 pF, 输入 50-MHz 50% 占空比方波 4
2侧最大功耗 (BL7142) PD2 130 mW VCC1=VCC2=5.5 V, TJ=150°C, CL=15 pF, 输入 50-MHz 50% 占空比方波 4
电源电压 (推荐工作条件) VDD1，VDD2 2.35 5.5 V 3
VDD电源电压上升时的欠压阈值 VDD（UVLO+） 1.75 2 V 3
VDD电源电压下降时的欠压阈值 VDD（UVLO-） 1.55 1.65 V 3
VDD迟滞欠压阈值 VHYS（UVLO） 10 70 230 mV 3
高电平输出电流 IOH -4 mA VDDO=5V 3
高电平输出电流 IOH -2 mA VDDO=3.3V 3
高电平输出电流 IOH -1 mA VDDO=2.5V 3
低电平输出电流 IOL 4 mA VDDO=5V 3
低电平输出电流 IOL 2 mA VDDO=3.3V 3
低电平输können出电流 IOL 1 mA VDDO=2.5V 3
输入阈值逻辑低电平 VIL 0 V 3
信号传输数率 DR 0 100 Mbps 3
环境温度 TA -40 25 125 ℃ 3
输出电压逻辑低电平 VOL 0.2 0.3 V IOL=4mA; 图7-1; VDD1=VDD2=5V±10% 5
输入高电平漏电流 IIH 5 μA VIH=VDDI, INx/ENx之间的电流; VDD1=VDD2=5V±10% 5
输入低电平漏电流 IIL -10 μA VIL=0V, INx/ENx之间的电流; VDD1=VDD2=5V±10% 5
共模瞬态抗扰度 CMTI 80 100 kV/μs 图7-2; VDD1=VDD2=5V±10% 5
输出电压逻辑低电平 VOL 0.06 0.1 V IOL=2mA; 图7-1; VDD1=VDD2=3.3V±10% 5
输出电压逻辑低电平 VOL 0.03 0.05 V IOL=1mA; 图7-1; VDD1=VDD2=2.5V±10% 5
传播延迟时间 (5V) tPLH，tPHL 7 11 15 ns 图 7-1; VDD1=VDD2=5V±10% 9
脉冲宽度失真 (5V) PWD 0.2 3 ns /tPLH-tPHL/; VDD1=VDD2=5V±10% 9
不同芯片间输出偏移时间 (5V) tsk(pp) 4.5 ns 同方向输入不同芯片之间 (注a); VDD1=VDD2=5V±10% 9
关闭使能传播延迟 高电平至高阻 (5V) tPHZ 20 28 ns 输出高电平至输出高阻抗; VDD1=VDD2=5V±10% 9
关闭使能传播延迟 低电平至高阻 (5V) tPLZ 18 24 ns 输出低电平至输出高阻抗; VDD1=VDD2=5V±10% 9
开启使能传播延迟 高阻至高电平 (5V, WH) tPZH 7 13 ns BL714xWH; VDD1=VDD2=5V±10% 9
开启使能传播延迟 高阻至低电平 (5V, WH) tPZL 1.3 2 μs BL714xWH; VDD1=VDD2=5V±10% 9
传播延迟时间 (3.3V) tPLH，tPHL 7 11 15 ns 图 7-1; VDD1=VDD2=3.3V±10% 9
脉冲宽度失真 (3.3V) PWD 0.2 3 ns /tPLH-tPHL/; VDD1=VDD2=3.3V±10% 9
不同芯片间输出偏移时间 (3.3V) tsk(pp) 4.5 ns 同方向输入不同芯片之间 (注a); VDD1=VDD2=3.3V±10% 9
关闭使能传播延迟 高电平至高阻 (3.3V) tPHZ 25 32 ns 输出高电平至输出高阻抗; VDD1=VDD2=3.3V±10% 9
关闭使能传播延迟 低电平至高阻 (3.3V) tPLZ 8 14 ns 输出低电平至输出高阻抗; VDD1=VDD2=3.3V±10% 9
开启使能传播延迟 高阻至高电平 (3.3V, WH) tPZH 10 15 ns BL714xWH; VDD1=VDD2=3.3V±10% 9
开启使能传播延迟 高阻至低电平 (3.3V, WH) tPZL 1.2 2 μs BL714xWH; VDD1=VDD2=3.3V±10% 9
传播延迟时间 (2.5V) tPLH，tPHL 9 13 17 ns 图 7-1; VDD1=VDD2=2.5V±10% 10
脉冲宽度失真 (2.5V) PWD 0.2 3 ns /tPLH-tPHL/; VDD1=VDD2=2.5V±10% 10
不同芯片间输出偏移时间 (2.5V) tsk(pp) 4.5 ns 同方向输入不同芯片之间 (注a); VDD1=VDD2=2.5V±10% 10
关闭使能传播延迟 高电平至高阻 (2.5V) tPHZ 31 37 ns 输出高电平至输出高阻抗; VDD1=VDD2=2.5V±10% 10
关闭使能传播延迟 低电平至高阻 (2.5V) tPLZ 10 15 ns 输出低电平至输出高阻抗; VDD1=VDD2=2.5V±10% 10
开启使能传播延迟 高阻至高电平 (2.5V, WH) tPZH 16 22 ns BL714xWH; VDD1=VDD2=2.5V±10% 10
开启使能传播延迟 高阻至低电平 (2.5V, WH) tPZL 1.2 2 μs BL714xWH; VDD1=VDD2=2.5V±10% 10
高电平输出电压 阈值迟滞 (5V) VI(HYS) 1.24 V VDD1=VDD2=5V±10% 5
输入阈值迟滞 (3.3V) VI(HYS) 0.9 V VDD1=VDD2=3.3V±10% 5
输入阈值迟滞 (2.5V) VI(HYS) 0.85 V VDD1=VDD2=2.5V±10% 5

CAD (KiCad official)

  • Symbol: BL7142WH
  • Footprint: Package_SO:SOIC-16_3.9x9.9mm_P1.27mm
  • 3D model: SOIC-16-300mil (KiCad packages3D, STEP)
  • 3D model files: bl7142wh-etched.step / bl7142wh-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); bl7142wh.step / bl7142wh.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: BL Shanghai Belling datasheet (15 pp, sha256 9788329c897a81df, retrieved 2026-10-19, tier: lcsc)
  • Datasheet language: Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF