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docs bl7141wh: re-etch, flat white mark read from pin 1 (service-occt 1.4.0) + chip hero · Ray 1mo ago
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bl7141wh-etched.fit.json bl7141wh: re-etch, flat white mark read from pin 1 (service-occt 1.4.0) + chip hero · Ray 1mo ago
bl7141wh-etched.glb bl7141wh: re-etch, flat white mark read from pin 1 (service-occt 1.4.0) + chip hero · Ray 1mo ago
bl7141wh-etched.step bl7141wh: re-etch, flat white mark read from pin 1 (service-occt 1.4.0) + chip hero · Ray 1mo ago
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README.md bl7141wh: laser-etched CAD + chip hero (factory 2.0.0 backfill) · Ray 1mo ago

BL7141WH

BL Shanghai Belling · Digital Isolators · SOIC-16-300mil

BL7141WH from BL Shanghai Belling, in a SOIC-16-300mil. Pinout and pin descriptions extracted from the manufacturer datasheet by ds2sf; symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 VDD1 power_in Side-1 supply, 2.5 V to 5.5 V. Bypass to GND1 with 100 nF placed within 2 mm.
2 GND1 power_in Side-1 reference ground. Common to pin 8 internally.
3 VIA input Channel A digital input (side 1 → side 2 forward). Logic level referenced to VDD1: VIH = 0.7 x VDD1, VIL = 0.25 x VDD1.
4 VIB input Channel B digital input (side 1 → side 2 forward). Logic level referenced to VDD1.
5 VIC input Channel C digital input (side 1 → side 2 forward). Logic level referenced to VDD1.
6 VOD output Channel D digital output on side 1 (reverse channel, side 2 → side 1). Drive strength at 5 V: IOH = -4 mA, IOL = 4 mA. Default state is HIGH (WH variant) when input floats or VDDI is unpowered.
7 EN1 input Side-1 output enable. Active high or floating enables side-1 outputs (pin 6 VOD on BL7141); tie low to place side-1 outputs in high-impedance (Z) state.
8 GND1 power_in Side-1 reference ground (second GND1 pin, common with pin 2).
9 GND2 power_in Side-2 reference ground. Isolated from GND1 by the SiO2 barrier (5 kVrms working, 8 kVpk transient).
10 EN2 input Side-2 output enable. Active high or floating enables side-2 outputs (VOA, VOB, VOC); tie low to place side-2 outputs in high-impedance (Z) state.
11 VID input Channel D digital input on side 2 (reverse channel, side 2 → side 1). Logic level referenced to VDD2.
12 VOC output Channel C digital output on side 2 (forward channel). Drive strength at 5 V: IOH = -4 mA, IOL = 4 mA. Default HIGH (WH variant) when VIC is floating or VDDI is unpowered.
13 VOB output Channel B digital output on side 2 (forward). Default HIGH (WH variant) on floating input or unpowered VDDI.
14 VOA output Channel A digital output on side 2 (forward). Default HIGH (WH variant) on floating input or unpowered VDDI.
15 GND2 power_in Side-2 reference ground (second GND2 pin, common with pin 9).
16 VDD2 power_in Side-2 supply, 2.5 V to 5.5 V. Bypass to GND2 with 100 nF placed within 2 mm.

Key specifications

Parameter Value
Manufacturer BL Shanghai Belling
Package SOIC-16-300mil
Category Comm/UART
Pins 16

Ordering variants

Same part, different packaging or reel option.

  • BL7141WH
  • BL7141WL
  • BL7140WH
  • BL7140WL
  • BL7142WH
  • BL7142WL

CAD (KiCad official)

  • Symbol: BL7141WH
  • Footprint: Package_SO:SOIC-16_3.9x9.9mm_P1.27mm
  • 3D model: SOIC-16-300mil (KiCad packages3D, STEP)
  • 3D model files: bl7141wh-etched.step / bl7141wh-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); bl7141wh.step / bl7141wh.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: BL Shanghai Belling datasheet (15 pp, sha256 1bc81353fbdb9441, retrieved 2026-08-17, tier: lcsc)
  • Datasheet language: Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
  • Extractor: ds2sf (Claude). Every pin and dimension is cited to a datasheet page; it refuses to fabricate.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF