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docs bl7121ah: re-etch, flat white mark read from pin 1 (service-occt 1.4.0) + chip hero · Ray 1mo ago
viewers bl7121ah: viewers · Ray 2mo ago
bl7121ah-etched.fit.json bl7121ah: re-etch, flat white mark read from pin 1 (service-occt 1.4.0) + chip hero · Ray 1mo ago
bl7121ah-etched.glb bl7121ah: re-etch, flat white mark read from pin 1 (service-occt 1.4.0) + chip hero · Ray 1mo ago
bl7121ah-etched.step bl7121ah: re-etch, flat white mark read from pin 1 (service-occt 1.4.0) + chip hero · Ray 1mo ago
bl7121ah.glb Publish 0.1.0 · Ray 2mo ago
bl7121ah.kicad_mod Publish 0.1.0 · Ray 2mo ago
bl7121ah.kicad_sym Publish 0.1.0 · Ray 2mo ago
bl7121ah.lbr Publish 0.1.0 · Ray 2mo ago
bl7121ah.step Publish 0.1.0 · Ray 2mo ago
package.json Publish 0.2.0 · Ray 2mo ago
page.json bl7121ah: component.models_3d pose record per STEP (Z-up, seated z=0, pad-centre origin, identity binding) · Ray 28d ago
README.md bl7121ah: laser-etched CAD + chip hero (factory 2.0.0 backfill) · Ray 1mo ago

BL7121AH

BL Shanghai Belling · Digital Isolators · SOIC-8

BL7121AH from BL Shanghai Belling, in a SOIC-8. Pinout and pin descriptions extracted from the manufacturer datasheet by ds2sf; symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 VDD1 power_in Side 1 power supply, 2.5 V to 5.5 V (recommended). Requires a 0.1 uF bypass capacitor to GND1 close to the pin. Absolute max 6 V.
2 VOA output Channel A digital output on side 1 (reverse channel). Referenced to VDD1/GND1. Drives IOH up to -4 mA / IOL up to 4 mA at 5 V supply. Default state is HIGH (AH suffix) when input power or signal is lost.
3 VIB input Channel B digital input on side 1 (forward channel). Referenced to VDD1/GND1. VIH >= 0.7VDD1, VIL <= 0.25VDD1. High-Z if left open (output goes to default HIGH state).
4 GND1 power_in Ground reference for side 1 (VDD1 domain). Isolated from GND2 by the SiO2 capacitive barrier (up to 3750 VRMS working isolation).
5 GND2 power_in Ground reference for side 2 (VDD2 domain). Isolated from GND1 by the SiO2 capacitive barrier.
6 VOB output Channel B digital output on side 2 (forward channel). Referenced to VDD2/GND2. Drives IOH up to -4 mA / IOL up to 4 mA at 5 V supply. Default state is HIGH (AH suffix) when input power or signal is lost.
7 VIA input Channel A digital input on side 2 (reverse channel). Referenced to VDD2/GND2. VIH >= 0.7VDD2, VIL <= 0.25VDD2. High-Z if left open (output goes to default HIGH state).
8 VDD2 power_in Side 2 power supply, 2.5 V to 5.5 V (recommended). Requires a 0.1 uF bypass capacitor to GND2 close to the pin. Absolute max 6 V.

Key specifications

Parameter Value
Manufacturer BL Shanghai Belling
Package SOIC-8
Category Comm/UART
Pins 8

Ordering variants

Same part, different packaging or reel option.

  • BL7121AH

CAD (KiCad official)

  • Symbol: BL7121AH
  • Footprint: Package_SO:SOIC-8_3.9x4.9mm_P1.27mm
  • 3D model: SOIC-8 (KiCad packages3D, STEP)
  • 3D model files: bl7121ah-etched.step / bl7121ah-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); bl7121ah.step / bl7121ah.glb are the bare package body.

3D model downloads

Two STEP files. Same geometry, different body top:

File Size Use it when
bl7121ah.step 122 KB You want the bare part, or you mark your own boards.
bl7121ah-etched.step 1.4 MB You want the part with BL7121AH already on it.

The marking in the etched file is real recessed geometry cut into the solid, not a texture or a decal: 366 faces against 147 in the bare model. It survives export, section views, and rendering in any CAD tool, and it drops straight into KiCad or Fusion with no extra setup.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: BL Shanghai Belling datasheet (13 pp, sha256 b22900b73aef2795, retrieved 2026-08-17, tier: lcsc)
  • Extractor: ds2sf (Claude). Every pin and dimension is cited to a datasheet page; it refuses to fabricate.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF