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BL6513
Public Made by Adomby adom
BL(Shanghai Belling) Energy Metering ICs, SOP-24. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
Generated by kicad-footprint-generator · KiCad file format 20260206
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BL6513
BL(Shanghai Belling) · Energy Metering ICs · SOP-24
BL6513 from BL(Shanghai Belling), in a SOP-24. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | CF | output | High-frequency calibration pulse output whose frequency is proportional to average active power, selectable via SCF/S1/S0 (VOH 4.4 V min, VOL 0.5 V max at 10 mA). |
| 2 | DGND | power_in | Ground reference for the internal digital circuits. |
| 3 | VDD | power_in | Positive +5 V supply for analog and digital sections, to be kept within +4.75 V to +5.25 V in normal operation. |
| 4 | REVP | output | Reverse active power indicator, goes high when the current/voltage phase difference exceeds 90° in any phase (VOH 4.4 V min, VOL 0.5 V max at 10 mA). |
| 5 | IAP | input | Positive input of phase A current sampling signal, maximum differential input voltage ±500 mV. |
| 6 | IAN | input | Negative input of phase A current sampling signal, maximum differential input voltage ±500 mV. |
| 7 | IBP | input | Positive input of phase B current sampling signal, maximum differential input voltage ±500 mV. |
| 8 | IBN | input | Negative input of phase B current sampling signal, maximum differential input voltage ±500 mV. |
| 9 | ICP | input | Positive input of phase C current sampling signal, maximum differential input voltage ±500 mV. |
| 10 | ICN | input | Negative input of phase C current sampling signal, maximum differential input voltage ±500 mV. |
| 11 | AGND | power_in | Ground reference for the internal analog circuits. |
| 12 | REF | bidirectional | Reference voltage output/input, on-chip reference 2.42 V ±8% with typical 30 ppm/°C, external 2.5 V input allowed, 100 µF capacitor recommended against burst interference. |
| 13 | VN | input | Negative input of the three-phase voltage sampling signals, reference for VAP/VBP/VCP, maximum differential input ±500 mV. |
| 14 | VCP | input | Positive input of phase C voltage sampling signal relative to VN, maximum differential input ±500 mV. |
| 15 | VBP | input | Positive input of phase B voltage sampling signal relative to VN, maximum differential input ±500 mV. |
| 16 | VAP | input | Positive input of phase A voltage sampling signal relative to VN, maximum differential input ±500 mV. |
| 17 | ADDSEL | input | Selects power summation mode: 0 selects absolute-value sum, 1 selects algebraic sum. |
| 18 | SCF | input | High-frequency calibration pulse select input that together with S1 and S0 selects the CF output frequency. |
| 19 | CLKIN | input | External clock input, or crystal connection to CLKOUT (3.58 MHz used in the specifications). |
| 20 | CLKOUT | output | Clock drive pin, or crystal connection to CLKIN. |
| 21 | S0 | input | Mode select input that with S1 and SCF selects the working mode for different meter constants. |
| 22 | S1 | input | Mode select input that with S0 and SCF selects the working mode for different meter constants. |
| 23 | F1 | output | Low-speed non-overlapping logic output with frequency proportional to average active power, able to drive an electromechanical counter or two-phase stepper motor (10 mA). |
| 24 | F2 | output | Low-speed non-overlapping logic output with frequency proportional to average active power, able to drive an electromechanical counter or two-phase stepper motor (10 mA). |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | BL(Shanghai Belling) |
| Package | SOP-24 |
| Category | ADC/DAC/Data Conversion |
| Pins | 24 |
Electrical characteristics
Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Supply voltage | VDD | -0.3 | 5.3 | V | T=25℃ | 3 | |
| Operating temperature | Topr | -40 | 85 | ℃ | T=25℃ | 3 | |
| Storage temperature | Tstr | -55 | 150 | ℃ | T=25℃ | 3 | |
| Power dissipation (SOP24) | 400 | mW | T=25℃ | 3 | |||
| Supply voltage (normal operation) | VDD | 4.75 | 5 | 5.25 | V | Pin 3 | 2 |
| Supply current | IVDD | 7 | mA | T=25℃, VDD=5V, CLKIN=3.58MHz, Pin3 | 3 | ||
| Input high level (SCF,S0,S1,ADDSEL) | VIH | 4 | V | VDD=5V | 3 | ||
| Input low level (SCF,S0,S1,ADDSEL) | VIL | 1 | V | VDD=5V | 3 | ||
| Input capacitance (logic) | CIN | 10 | pF | VDD=5V | 3 | ||
| Output high level F1,F2 | VOH1 | 4.4 | V | IH=10mA | 3 | ||
| Output low level F1,F2 | VOL1 | 0.5 | V | IL=10mA | 3 | ||
| Output current F1,F2 | IO1 | 10 | mA | 3 | |||
| Output high level CF,REVP | VOH2 | 4.4 | V | IH=10mA | 3 | ||
| Output low level CF,REVP | VOL2 | 0.5 | V | IL=10mA | 3 | ||
| Output current CF,REVP | IO2 | 10 | mA | 3 | |||
| Reference voltage | Vref | 2.3 | 2.42 | 2.6 | V | VDD=5V, Pin12 | 4 |
| Reference temperature coefficient | 30 | 60 | ppm/°C | Pin12 | 4 | ||
| Max analog input level | VAIN | -500 | 500 | mV | 4 | ||
| DC input impedance | 330 | Kohm | 4 | ||||
| Analog input capacitance | 6 | 10 | pF | 4 | |||
| ADC offset | Voff | -15 | 15 | mV | 4 | ||
| Current channel nonlinearity error | 0.1 | 0.3 | % | Current channel input ±500mV; dynamic range 1000:1, Pin1 | 4 | ||
| Phase error, current leading 37° (PF=0.8 capacitive) | 0.1 | 0.3 | % | Pin1 | 4 | ||
| Phase error, current lagging 60° (PF=0.5 inductive) | 0.1 | 0.3 | % | Pin1 | 4 | ||
| Positive/negative active power error | ENP | 0.3 | % | Vv=±110mV, V(I)=2mV, cosϕ=1; cosϕ=-1, Pin1 | 4 | ||
| Gain error | 5 | 7 | % | Pin1 | 4 | ||
| Power-down detection level | Vdown | 3.9 | 4 | 4.1 | V | Supply varies 3.5V~5V, full-scale current/voltage channel input | 4 |
| F1/F2 high pulse width | t1 | 145 | ms | VDD=5V, CLKIN=3.58MHz, -40~+85°C, low power | 5 | ||
| CF high pulse width | t4 | 90 | ms | low power metering | 5 |
CAD (KiCad official)
- Symbol:
BL6513 - Footprint:
Package_SO:SOP-24_7.5x15.4mm_P1.27mm - 3D model: SOP-24, generated from the KiCad footprint (body from the F.Fab outline, terminals on the pads, 2.65 mm nominal SOIC height). Neither the vendor nor KiCad ships a 3D model for this package, so the dimensions are nominal, not the manufacturer's CAD (STEP)
- 3D model files:
bl6513-etched.step/bl6513-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);bl6513.step/bl6513.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: BL(Shanghai Belling) datasheet (12 pp, sha256
5b150b2415331576, retrieved 2026-10-23, tier: lcsc) - Datasheet language: Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
- Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-sonnet-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).