component
BL25CM1A-PARC
Public Made by Adomby adom
BL Shanghai Belling EEPROM, SOP-8. Datasheet-verified pinout, KiCad symbol/footprint/3D.
3D Model
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Symbol & Footprint
Schematic Symbol
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PCB Footprint
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Datasheet
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README
markdownBL25CM1A-PARC
BL Shanghai Belling · EEPROM · SOP-8
BL25CM1A-PARC from BL Shanghai Belling, in a SOP-8. Pinout and pin descriptions extracted from the manufacturer datasheet by ds2sf; symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | /CS | input | SPI Chip Select, active low. When /CS is high, the device is deselected and SO is placed at high impedance; power consumption drops to standby unless an internal write cycle is in progress. Driving /CS low selects the device so that instructions can be clocked in on SI. After power-up, /CS must transition high to low before a new instruction is accepted. |
| 2 | SO | output | SPI Serial Data Output. Data or status is shifted out of this pin on the falling edge of SCK. SO is placed at high impedance when the device is deselected (/CS high) or when /HOLD is asserted low. |
| 3 | /WP | input | Write Protect, active low. Used together with the Status Register Write Disable (SRWD) bit to enable the Hardware Protected mode: when SRWD = 1 and /WP is driven low, writes to the Status Register and to block-protected memory are inhibited. Tie high to disable hardware write protection. |
| 4 | VSS | power_in | Ground reference for supply and all signals. Connect to the system ground plane. |
| 5 | SI | input | SPI Serial Data Input. Instructions, addresses and write data are clocked into the device on the rising edge of SCK. |
| 6 | SCK | input | SPI Serial Clock Input. Provides the timing for serial input and output operations; SI is sampled on the rising edge and SO changes on the falling edge. Supports SPI modes (0,0) and (1,1); maximum frequency is 2 MHz for BL25CM1A and 5 MHz for BL25CM1A5. |
| 7 | /HOLD | input | Hold input, active low. Pausing the device while it is actively selected: when /HOLD is low while /CS is also low, SO is placed at high impedance and signals on SI and SCK are ignored (don't care). Driving /HOLD high resumes device operation. Useful when multiple devices share the SPI bus; tie high if unused. |
| 8 | VCC | power_in | Power supply, 2.8 V to 5.5 V. Decouple to VSS with a local bypass capacitor (typically 100 nF) close to the pin. |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | BL Shanghai Belling |
| Package | SOP-8 |
| Category | Memory |
| Pins | 8 |
Ordering variants
Same part, different packaging or reel option.
BL25CM1A-PARC
CAD (KiCad official)
- Symbol:
BL25CM1A-PARC - Footprint:
Package_SO:SOIC-8_3.9x4.9mm_P1.27mm - 3D model: SOP-8 (KiCad packages3D, STEP)
- 3D model files:
bl25cm1a-parc-etched.step/bl25cm1a-parc-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);bl25cm1a-parc.step/bl25cm1a-parc.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: BL Shanghai Belling datasheet (21 pp, sha256
ff7e0e771d288dc6, retrieved 2026-08-17, tier: lcsc) - Extractor:
ds2sf(Claude). Every pin and dimension is cited to a datasheet page; it refuses to fabricate. - CAD: KiCad official libraries (CC-BY-SA 4.0).