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Contents

README

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BIN1044S-C

BORN · CAN Transceivers · SOIC-8

BIN1044S-C from BORN, in a SOIC-8. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 TXD input Transmit data input: high or floating drives the CAN bus recessive, low drives it dominant, and it has an internal pull-up.
2 GND power_in Reference ground for the transceiver.
3 VCC power_in 5 V supply input (recommended 4.5 V to 5.5 V); place a 0.1 µF capacitor between VCC and GND as close to the device as possible.
4 RXD output Receiver data output referenced to VIO: high when the bus is recessive and low when the bus is dominant, with recommended IOH of -2 mA and IOL of 2 mA.
5 NC unconnected Not connected on the BIN1044 (-C) variant; pin 5 is VIO only on the BIN1044V version.
6 CANL bidirectional Low-level CAN bus line, with bus fault protection of ±58 V.
7 CANH bidirectional High-level CAN bus line, with bus fault protection of ±58 V.
8 STB input Standby mode control: high selects standby mode, low selects normal mode, and it has an internal pull-up.

Key specifications

Parameter Value
Manufacturer BORN
Package SOIC-8
Category Interface
Pins 8

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
VCC 5V supply voltage VCC -0.3 7 V 3
CAN bus I/O voltage (CANH, CANL) VBUS -58 58 V 3
Maximum differential voltage CANH to CANL V(DIFF) -58 58 V 3
Logic-side input voltage (TXD, STB) V(Logic_Input) -0.3 7 V 3
Logic-side output voltage (RXD) V(Logic_Output) -0.3 7 V 3
RXD receiver output current IO(RXD) -8 8 mA 3
Junction temperature TJ -55 150 ◦C 3
Storage temperature TSTG -65 150 ◦C 3
VCC 5V bus supply voltage VCC 4.5 5.5 V 3
RXD high-level output current IOH(RXD) -2 mA 3
RXD low-level output current IOL(RXD) 2 mA 3
IC junction-to-ambient thermal resistance (SOIC8 column) RθJA 170 ◦C/W 3
5V supply current, dominant ICC 45 70 mA TXD = 0V, STB=0V, RL=60Ω (dominant) 4
5V supply current, recessive ICC 4.5 7.5 mA TXD = VCC, STB=0V, RL=50Ω (recessive) 4
5V supply current, standby (BIN1044) 22 35 μA TXD=STB=VCC (standby mode, BIN1044), RL=50Ω 4
VCC UVLO voltage, rising VUV_VCC 4.2 4.45 V rising 4
VCC UVLO voltage, falling VUV_VCC 3.65 4 4.4 V falling 4
VCC protection-state voltage (BIN1044), rising VUV_VCC_sd 1.56 1.9 V rising 4
VCC protection-state voltage (BIN1044), falling VUV_VCC_sd 1.3 1.51 1.85 V falling 4
STB input high leakage current IIH -2 2 uA STB=VCC=5.5V 4
STB input low leakage current IIL -200 -100 -20 uA STB=0V, VCC=5.5V 4
TXD input high leakage current IIH -2.5 1 uA TXD = VCC = 5.5V 4
TXD input low leakage current IIL -200 -100 -20 uA TXD = 0V, VCC = 5.5V 4
Single-ended dominant output voltage, CANH VO(DOM) 2.75 4.5 V TXD=low, STB=0V, RL=50-65Ω, CANH port 5
Single-ended dominant output voltage, CANL VO(DOM) 0.5 2.25 V TXD=low, STB=0V, RL=50-65Ω, CANL port 5
Differential dominant output voltage VOD(DOM) 1.4 3.3 V TXD=low, STB=0V, RL=45-70Ω, RCM open 5
Differential dominant output voltage VOD(DOM) 1.5 3 V TXD=low, STB=0V, RL=50-65Ω, RCM open 5
Single-ended recessive output voltage, CANH VO(REC) 2 3 V TXD=high, STB=0V, no load, CANH port 5
Single-ended recessive output voltage, CANL VO(REC) 2 3 V TXD=high, STB=0V, no load, CANL port 5
Differential recessive output voltage VOD(REC) -120 12 mV TXD=high, STB=0V, RL=60Ω 5
Standby bus voltage, CANH VO(STB) -0.1 0.1 V STB=VCC, RL open, CANH 5
Standby bus voltage, CANL VO(STB) -0.1 0.1 V STB=VCC, RL open, CANL 5
Standby bus voltage, CANH-CANL VO(STB) -0.2 0.2 V STB=VCC, RL open, CANH-CANL 5
Dominant short-circuit current, CANH IOS(SS_DOM) -115 mA TXD=low, STB=0V, CANL open, CANH from -15V to 40V, Fig 9 5
Dominant short-circuit current, CANL IOS(SS_DOM) 115 mA TXD=low, STB=0V, CANH open, CANL from -15V to 40V, Fig 9 5
Recessive short-circuit current IOS(SS_rec) -6 6 mA TXD=high, STB=0V, VBUS from -27V to 32V, Fig 9 5
Transient symmetry (dominant and recessive) Vsys 0.9 1.1 V/V RL=60Ω, STB=0V, Csplit=4.7nF, RCM open, Txd=250kHz, 1MHz, 2.5MHz, Fig 3 5
DC symmetry (dominant and recessive) Vsys_dc -0.4 0.4 V RL=60Ω, STB=0V, RCM open, Fig 3 5
Over-temperature protection threshold TSTD 190 ◦C 5
Common-mode input range, normal mode VCM -30 30 V normal mode, RXD output valid, Fig 4 5
Common-mode input range, standby mode VCM -20 20 V standby mode, RXD output valid, Fig 4 5
Normal-mode input threshold voltage VIT 500 900 mV STB=0V, Vcm from -20V to 20V, Fig 4 5
Normal-mode differential input threshold (dominant) VDIFF_D 0.9 9 V STB=0V, Vcm from -20V to 20V, Fig 4 5
Normal-mode differential input threshold (recessive) VDIFF_R -4 0.5 V STB=0V, Vcm from -20V to 20V, Fig 4 6
Standby-mode differential input threshold (dominant) VDIFF_D(STB) 1.15 9 V STB=high, Vcm from -20V to 20V, Fig 4 6
Standby-mode differential input threshold (recessive) VDIFF_R(STB) -4 0.4 V STB=high, Vcm from -20V to 20V, Fig 4 6
CANH/CANL input resistance RIN 20 45 kΩ TXD=high, STB=0V, Vcm from -30V to 30V 6
Differential input resistance RDIFF 40 90 kΩ TXD=high, STB=0V, Vcm from -30V to 30V 6
Input leakage current ILKG 8 uA VCC = 0V, VCANH=5V 6
Dominant timeout (TXD) tDOM 2 5 8 ms RL=60Ω, CL open, Fig 6 7
Wake-up valid filter time Twk_FILTER 0.5 1.8 us Fig 13 7
Bus wake-up timeout Twk_FILTEROUT 0.8 6 ms Fig 13 7
Loop delay, recessive to dominant tloop1 125 210 ns recessive to dominant, RL=60Ω, CL=100pF, Fig 5 7
Loop delay, dominant to recessive tloop2 150 210 ns dominant to recessive, RL=60Ω, CL=100pF, Fig 5 7
Bit time on bus side (standard) Tbit(bus) 450 530 ns STB=0V, bus side RL=60Ω, CL=100pF, CRXD=15pF, Fig 8 7
Bit time on bus side (high-speed) Tbit(bus) 155 210 ns STB=0V, bus side RL=60Ω, CL=100pF, CRXD=15pF, high-speed version, Fig 8 7
Bit time on receiver side (high-speed) Tbit(rxd) 120 220 ns STB=0V, receiver side RL=60Ω, CL=100pF, CRXD=15pF, high-speed version, Fig 8 7
Receiver pulse distortion (standard) Trec -50 20 ns STB=0V, receiver side RL=60Ω, CL=100pF, CRXD=15pF, Fig 8 7
Receiver pulse distortion (high-speed) Trec -45 15 ns STB=0V, receiver side RL=60Ω, CL=100pF, CRXD=15pF, high-speed version, Fig 8 7

CAD (KiCad official)

  • Symbol: BIN1044S-C
  • Footprint: Package_SO:SOIC-8_3.9x4.9mm_P1.27mm
  • 3D model: SOIC-8 (KiCad packages3D, STEP)
  • 3D model files: bin1044s-c-etched.step / bin1044s-c-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); bin1044s-c.step / bin1044s-c.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: BORN datasheet (18 pp, sha256 1e00d950cb0ed0bc, retrieved 2026-10-18, tier: lcsc)
  • Datasheet language: Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF