component
BD9P135EFV-CE2
Public Made by Adomby adom
ROHM Semicon DC-DC Converters, HTSSOP-20-EP. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
main
BD9P135EFV-CE2
ROHM Semicon · DC-DC Converters · HTSSOP-20-EP
BD9P135EFV-CE2 from ROHM Semicon, in a HTSSOP-20-EP. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | EN | input | Enable pin: apply 0.8 V or lower to disable the device and 2.0 V or higher to enable it; this pin must not be left open. |
| 2 | VIN | power_in | Power supply input for the internal circuit; connect this pin to the PVIN pins. |
| 3 | PVIN | power_in | Power supply input for the switching regulator output stage; connect input ceramic capacitors (see page 33) between these pins and PGND. |
| 4 | PVIN | power_in | Power supply input for the switching regulator output stage; connect input ceramic capacitors (see page 33) between these pins and PGND. |
| 5 | N.C. | unconnected | Not connected to the chip; leave open, and confirm application behaviour if this pin is used and adjacent pins may be shorted. |
| 6 | PGND | power_in | Ground pin for the output stage of the switching regulator. |
| 7 | PGND | power_in | Ground pin for the output stage of the switching regulator. |
| 8 | SW | output | Switching node connected to the internal high-side FET source and low-side FET drain; connect the power inductor and bootstrap capacitor here. |
| 9 | SW | output | Switching node connected to the internal high-side FET source and low-side FET drain; connect the power inductor and bootstrap capacitor here. |
| 10 | BST | passive | Connect a 0.1 µF (Typ) bootstrap capacitor between this pin and SW; the voltage across it is the high-side FET gate drive. |
| 11 | OCP_SEL | input | Selects the average-inductor-current OCP threshold: 1.250 A (Typ) when connected to VREG (High) or 0.625 A (Typ) when connected to GND (Low). |
| 12 | MODE | input | Selects FPWM mode (set high), AUTO mode (set low or open), or SYNC mode (apply a clock to this pin). |
| 13 | SSCG | input | Spread spectrum select: connect to VREG (High) to enable spread spectrum or to GND (Low) to disable it. |
| 14 | RESET | output | Open-drain reset output; connect a pull-up resistor to VREG or the supply within the RESET pin absolute maximum rating, with 5 kΩ to 100 kΩ recommended. |
| 15 | GND | power_in | Ground pin. |
| 16 | VOUT_DIS | input | Discharges the VOUT node when the discharge function is required (connect to VOUT); otherwise connect this pin to GND. |
| 17 | VOUT_SNS | input | Inverting input of GmAmp1 used for OVP, SCP and RESET detection and for setting the GmAmp2 output clamp and phase compensation; connect to the output voltage. |
| 18 | N.C. | unconnected | Not connected to the chip on this variant; leave open, and confirm application behaviour if this pin is used and adjacent pins may be shorted. |
| 19 | VCC_EX | power_in | Power supply input for the internal circuit; VREG is supplied from this pin when between 3.2 V (VTEXH max) and 5.65 V (VEXOVPL min) is applied, and it should be connected to GND if unused. |
| 20 | VREG | power_out | Outputs 3.3 V (Typ) for the internal circuit; connect a 1.0 µF (Typ) ceramic capacitor and do not add external loads other than OCP_SEL, MODE, SSCG and the RESET pull-up. |
| 21 | EP | passive | Exposed pad (from the footprint; not named in the datasheet pin table). |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | ROHM Semicon |
| Package | HTSSOP-20-EP |
| Category | Power Management ICs |
| Pins | 21 |
Electrical characteristics
Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Input Voltage | VVIN, VPVIN | -0.3 | 42 | V | 9 | ||
| EN Voltage | VEN | -0.3 | 42 | V | 9 | ||
| BST Voltage | VBST | -0.3 | 49 | V | 9 | ||
| Voltage from SW to BST | ΔVBST VSW | -0.3 | V | max printed as VSW + 7 | 9 | ||
| FB, RESET, MODE, SSCG, OCP_SEL Voltage | VFB, VRESET, VMODE, VSSCG, VOCP_SEL | -0.3 | 7 | V | 9 | ||
| VOUT_DIS Voltage | VVOUT_DIS | -0.3 | 10 | V | 9 | ||
| VOUT_SNS Voltage | VVOUT_SNS | -0.3 | 10 | V | 9 | ||
| VCC_EX Voltage | VVCC_EX | -0.3 | 7 | V | 9 | ||
| VREG Voltage | VREG | -0.3 | 7 | V | 9 | ||
| Storage Temperature Range | Tstg | -55 | 150 | ˚C | 9 | ||
| Maximum Junction Temperature | Tjmax | 150 | ˚C | 9 | |||
| Human Body Model (HBM) | VESD_HBM | -2 | 2 | kV | guaranteed by design, not tested | 9 | |
| Input Voltage | VVIN, VPVIN | 3.5 | 40 | V | 10 | ||
| Operating Temperature | Ta | -40 | 125 | ˚C | 10 | ||
| SW Minimum ON Time | tONMIN | 50 | ns | 10 | |||
| SW Minimum OFF Time | tOFFMIN | 130 | ns | VREG = 3.3 V | 10 | ||
| Output Current | IOUT | 1 | A | 10 | |||
| Input Capacitor (VIN Continuous Condition) | CIN | 2.3 | µF | VIN Continuous Condition | 10 | ||
| VREG Capacitor | CREG | 0.6 | 1 | 2 | µF | 10 | |
| BST Capacitor | CBST | 0.05 | 0.1 | 0.2 | µF | 10 | |
| Shutdown Current | ISDWN | 2.1 | 10 | µA | VEN = 0 V, Ta = -40 ˚C to +105 ˚C | 10 | |
| Quiescent Current from VIN | IQ_VIN1 | 2.1 | 6 | µA | VMODE = 0 V, VVCC_EX = 5 V, VFB = VFB1 x 1.04 (SLEEP) | 10 | |
| Quiescent Current from VIN | IQ_VIN2 | 15 | 30 | µA | VMODE = 0 V, VVCC_EX = 0 V, VFB = VFB1 x 1.04 (SLEEP) | 10 | |
| Quiescent Current from VIN | IQ_VIN3 | 33 | 66 | µA | VMODE = 5 V, VVCC_EX = 5 V, VFB = VFB1 x 1.04 (No SLEEP) | 10 | |
| Quiescent Current from VIN | IQ_VIN4 | 1200 | 2400 | µA | VMODE = 5 V, VVCC_EX = 0 V, VFB = VFB1 x 1.04 (No SLEEP) | 10 | |
| Quiescent Current from VCC_EX | IQ_VCC_EX1 | 16 | 60 | µA | VMODE = 0 V, VFB = VFB1 x 1.04 (SLEEP) | 10 | |
| Quiescent Current from VCC_EX | IQ_VCC_EX2 | 1500 | 3000 | µA | VMODE = 5 V, VFB = VFB1 x 1.04 (No SLEEP) | 10 | |
| VIN Power On Reset Rising | VPOR_R | 3.6 | 3.8 | 4 | V | VIN Sweep Up | 10 |
| VREG Under Voltage Lockout Falling | VUVLO_F | 2.7 | 2.85 | 3 | V | VREG Sweep Down | 10 |
| VREG Under Voltage Lockout Rising | VUVLO_R | 2.75 | 2.95 | 3.15 | V | VREG Sweep Up | 10 |
| EN Input Voltage High | VENH | 2 | 40 | V | 10 | ||
| EN Input Voltage Low | VENL | 0 | 0.8 | V | 10 | ||
| VREG Voltage | VREG | 3 | 3.3 | 3.6 | V | Voltage Follower; VVCC_EX = 0 V | 11 |
| VCC_EX Threshold Voltage High | VTEXH | 2.9 | 3.05 | 3.2 | V | VVCC_EX Sweep Up | 11 |
| VCC_EX OVP Threshold Voltage High | VEXOVPH | 5.85 | 6.2 | 6.55 | V | 11 | |
| VCC_EX OVP Threshold Voltage Low | VEXOVPL | 5.65 | 6 | 6.35 | V | 11 | |
| Switching Frequency | fSW | 2 | 2.2 | 2.4 | MHz | 11 | |
| Synchronization Frequency Range | fSW_EX | 1.8 | 2.4 | MHz | External Clock Input | 11 | |
| Switching Frequency (Spread Spectrum) | fSWSSR | 1.9 | 2.52 | MHz | VSSCG = 5 V | 11 | |
| High Side FET ON Resistance | RONH | 210 | 440 | mΩ | VBST-VSW = 3.3 V | 11 | |
| Low Side FET ON Resistance | RONL | 140 | 290 | mΩ | VVCC_EX = 3.3 V | 11 | |
| Over Current Protection Threshold | IOCP10 | 1 | 1.25 | 1.5 | A | VOCP_SEL = 5 V | 11 |
| Over Current Protection Threshold | IOCP05 | 0.5 | 0.625 | 0.75 | A | VOCP_SEL = 0 V | 11 |
| Output Voltage (BD9P135EFV-C), VOUT_SNS Voltage, PWM Mode | VOUT_SNS1 | 3.25 | 3.308 | 3.366 | V | VOUT_SNS Voltage, PWM Mode | 11 |
| Enter SLEEP State Voltage (BD9P135EFV-C) | VOUT_SNS2 | 3.275 | 3.349 | 3.424 | V | VOUT_SNS Rising, Light Load Mode | 11 |
| Exit SLEEP State Voltage (BD9P135EFV-C) | VOUT_SNS3 | 3.266 | 3.341 | 3.416 | V | VOUT_SNS Falling, Light Load Mode | 11 |
| Soft Start Time | tSS | 2.5 | 3 | 3.9 | ms | VFB1 x 0.1 to VFB1 x 0.9 | 11 |
| Reset Threshold Voltage Low (BD9P135EFV-C) | 3 | 3.065 | 3.13 | V | VOUT_SNS Sweep Down | 12 | |
| Reset Threshold Voltage High (BD9P135EFV-C) | 3.08 | 3.16 | 3.24 | V | VOUT_SNS Sweep Up | 12 | |
| Reset ON Resistance | RRST | 190 | 400 | Ω | VIN = 2 V, VEN = 0 V, IRESET = 1 mA | 12 | |
| Reset Active Time | tRSTNACT | 2 | 3.6 | 5 | ms | 12 | |
| VOUT_SNS OVP Threshold Voltage High (BD9P135EFV-C) | 3.402 | 3.541 | 3.693 | V | 12 | ||
| VOUT_SNS OVP Threshold Voltage Low (BD9P135EFV-C) | 3.321 | 3.455 | 3.609 | V | 12 | ||
| SCP Threshold Voltage High (BD9P135EFV-C) | 2.81 | 2.97 | 3.14 | V | VOUT_SNS Sweep Up | 12 | |
| SCP Threshold Voltage Low (BD9P135EFV-C) | 2.48 | 2.64 | 2.81 | V | VOUT_SNS Sweep Down | 12 | |
| Output Voltage for BD9P135EFV-C | VOUT | 3.3 | V | 10 | |||
| Junction to Ambient (1s board) | θJA | 143 | °C/W | 1s board (JESD51-3) | 9 | ||
| Junction to Ambient (2s2p board) | θJA | 26.8 | °C/W | 2s2p board (JESD51-5, 7) | 9 | ||
| Junction to Top Characterization Parameter (1s board) | ΨJT | 8 | °C/W | 1s board (JESD51-3) | 9 | ||
| Junction to Top Characterization Parameter (2s2p board) | ΨJT | 4 | °C/W | 2s2p board (JESD51-5, 7) | 9 |
Materials and finish
As the datasheet states them (page.json metadata.appearance; the 3D model's colours follow it).
| Part | Material | Colour / plating | Datasheet says | Page |
|---|---|---|---|---|
| housing | abs | Human Body Model (HBM)(Note 1) VESD_HBM ±2 kV Caution 1: Operating the IC over the absolute maximum ratings may damage the IC. The damage can either be a short circuit between pins or an open circuit | 9 | |
| contacts | copper | 7. To minimize the emission noise from switching node, the distance between the SW pins to inductor should be as short as possible and not to expand the copper area more than necessary. | 49 |
CAD (KiCad official)
- Symbol:
BD9P135EFV-CE2 - Footprint:
Package_SO:TSSOP-20-1EP_4.4x6.5mm_P0.65mm_EP2.15x3.35mm - 3D model: HTSSOP-20-EP, generated from the KiCad footprint (body from the F.Fab outline, terminals on the pads, 1.2 mm nominal TSSOP height). Neither the vendor nor KiCad ships a 3D model for this package, so the dimensions are nominal, not the manufacturer's CAD (STEP)
- 3D model files:
bd9p135efv-ce2-etched.step/bd9p135efv-ce2-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);bd9p135efv-ce2.step/bd9p135efv-ce2.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: ROHM Semicon datasheet (60 pp, sha256
f5977b9e0766c210, retrieved 2026-10-30, tier: manufacturer) - Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-haiku-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).
# BD9P135EFV-CE2
**ROHM Semicon** · DC-DC Converters · HTSSOP-20-EP
BD9P135EFV-CE2 from ROHM Semicon, in a HTSSOP-20-EP. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
## Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | EN | input | Enable pin: apply 0.8 V or lower to disable the device and 2.0 V or higher to enable it; this pin must not be left open. |
| 2 | VIN | power_in | Power supply input for the internal circuit; connect this pin to the PVIN pins. |
| 3 | PVIN | power_in | Power supply input for the switching regulator output stage; connect input ceramic capacitors (see page 33) between these pins and PGND. |
| 4 | PVIN | power_in | Power supply input for the switching regulator output stage; connect input ceramic capacitors (see page 33) between these pins and PGND. |
| 5 | N.C. | unconnected | Not connected to the chip; leave open, and confirm application behaviour if this pin is used and adjacent pins may be shorted. |
| 6 | PGND | power_in | Ground pin for the output stage of the switching regulator. |
| 7 | PGND | power_in | Ground pin for the output stage of the switching regulator. |
| 8 | SW | output | Switching node connected to the internal high-side FET source and low-side FET drain; connect the power inductor and bootstrap capacitor here. |
| 9 | SW | output | Switching node connected to the internal high-side FET source and low-side FET drain; connect the power inductor and bootstrap capacitor here. |
| 10 | BST | passive | Connect a 0.1 µF (Typ) bootstrap capacitor between this pin and SW; the voltage across it is the high-side FET gate drive. |
| 11 | OCP_SEL | input | Selects the average-inductor-current OCP threshold: 1.250 A (Typ) when connected to VREG (High) or 0.625 A (Typ) when connected to GND (Low). |
| 12 | MODE | input | Selects FPWM mode (set high), AUTO mode (set low or open), or SYNC mode (apply a clock to this pin). |
| 13 | SSCG | input | Spread spectrum select: connect to VREG (High) to enable spread spectrum or to GND (Low) to disable it. |
| 14 | RESET | output | Open-drain reset output; connect a pull-up resistor to VREG or the supply within the RESET pin absolute maximum rating, with 5 kΩ to 100 kΩ recommended. |
| 15 | GND | power_in | Ground pin. |
| 16 | VOUT_DIS | input | Discharges the VOUT node when the discharge function is required (connect to VOUT); otherwise connect this pin to GND. |
| 17 | VOUT_SNS | input | Inverting input of GmAmp1 used for OVP, SCP and RESET detection and for setting the GmAmp2 output clamp and phase compensation; connect to the output voltage. |
| 18 | N.C. | unconnected | Not connected to the chip on this variant; leave open, and confirm application behaviour if this pin is used and adjacent pins may be shorted. |
| 19 | VCC_EX | power_in | Power supply input for the internal circuit; VREG is supplied from this pin when between 3.2 V (VTEXH max) and 5.65 V (VEXOVPL min) is applied, and it should be connected to GND if unused. |
| 20 | VREG | power_out | Outputs 3.3 V (Typ) for the internal circuit; connect a 1.0 µF (Typ) ceramic capacitor and do not add external loads other than OCP_SEL, MODE, SSCG and the RESET pull-up. |
| 21 | EP | passive | Exposed pad (from the footprint; not named in the datasheet pin table). |
## Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | ROHM Semicon |
| Package | HTSSOP-20-EP |
| Category | Power Management ICs |
| Pins | 21 |
## Electrical characteristics
Limits as printed in the datasheet (page.json `metadata.characteristics` carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Input Voltage | VVIN, VPVIN | -0.3 | | 42 | V | | 9 |
| EN Voltage | VEN | -0.3 | | 42 | V | | 9 |
| BST Voltage | VBST | -0.3 | | 49 | V | | 9 |
| Voltage from SW to BST | ΔVBST VSW | -0.3 | | | V | max printed as VSW + 7 | 9 |
| FB, RESET, MODE, SSCG, OCP_SEL Voltage | VFB, VRESET, VMODE, VSSCG, VOCP_SEL | -0.3 | | 7 | V | | 9 |
| VOUT_DIS Voltage | VVOUT_DIS | -0.3 | | 10 | V | | 9 |
| VOUT_SNS Voltage | VVOUT_SNS | -0.3 | | 10 | V | | 9 |
| VCC_EX Voltage | VVCC_EX | -0.3 | | 7 | V | | 9 |
| VREG Voltage | VREG | -0.3 | | 7 | V | | 9 |
| Storage Temperature Range | Tstg | -55 | | 150 | ˚C | | 9 |
| Maximum Junction Temperature | Tjmax | | | 150 | ˚C | | 9 |
| Human Body Model (HBM) | VESD_HBM | -2 | | 2 | kV | guaranteed by design, not tested | 9 |
| Input Voltage | VVIN, VPVIN | 3.5 | | 40 | V | | 10 |
| Operating Temperature | Ta | -40 | | 125 | ˚C | | 10 |
| SW Minimum ON Time | tONMIN | | | 50 | ns | | 10 |
| SW Minimum OFF Time | tOFFMIN | | | 130 | ns | VREG = 3.3 V | 10 |
| Output Current | IOUT | | | 1 | A | | 10 |
| Input Capacitor (VIN Continuous Condition) | CIN | 2.3 | | | µF | VIN Continuous Condition | 10 |
| VREG Capacitor | CREG | 0.6 | 1 | 2 | µF | | 10 |
| BST Capacitor | CBST | 0.05 | 0.1 | 0.2 | µF | | 10 |
| Shutdown Current | ISDWN | | 2.1 | 10 | µA | VEN = 0 V, Ta = -40 ˚C to +105 ˚C | 10 |
| Quiescent Current from VIN | IQ_VIN1 | | 2.1 | 6 | µA | VMODE = 0 V, VVCC_EX = 5 V, VFB = VFB1 x 1.04 (SLEEP) | 10 |
| Quiescent Current from VIN | IQ_VIN2 | | 15 | 30 | µA | VMODE = 0 V, VVCC_EX = 0 V, VFB = VFB1 x 1.04 (SLEEP) | 10 |
| Quiescent Current from VIN | IQ_VIN3 | | 33 | 66 | µA | VMODE = 5 V, VVCC_EX = 5 V, VFB = VFB1 x 1.04 (No SLEEP) | 10 |
| Quiescent Current from VIN | IQ_VIN4 | | 1200 | 2400 | µA | VMODE = 5 V, VVCC_EX = 0 V, VFB = VFB1 x 1.04 (No SLEEP) | 10 |
| Quiescent Current from VCC_EX | IQ_VCC_EX1 | | 16 | 60 | µA | VMODE = 0 V, VFB = VFB1 x 1.04 (SLEEP) | 10 |
| Quiescent Current from VCC_EX | IQ_VCC_EX2 | | 1500 | 3000 | µA | VMODE = 5 V, VFB = VFB1 x 1.04 (No SLEEP) | 10 |
| VIN Power On Reset Rising | VPOR_R | 3.6 | 3.8 | 4 | V | VIN Sweep Up | 10 |
| VREG Under Voltage Lockout Falling | VUVLO_F | 2.7 | 2.85 | 3 | V | VREG Sweep Down | 10 |
| VREG Under Voltage Lockout Rising | VUVLO_R | 2.75 | 2.95 | 3.15 | V | VREG Sweep Up | 10 |
| EN Input Voltage High | VENH | 2 | | 40 | V | | 10 |
| EN Input Voltage Low | VENL | 0 | | 0.8 | V | | 10 |
| VREG Voltage | VREG | 3 | 3.3 | 3.6 | V | Voltage Follower; VVCC_EX = 0 V | 11 |
| VCC_EX Threshold Voltage High | VTEXH | 2.9 | 3.05 | 3.2 | V | VVCC_EX Sweep Up | 11 |
| VCC_EX OVP Threshold Voltage High | VEXOVPH | 5.85 | 6.2 | 6.55 | V | | 11 |
| VCC_EX OVP Threshold Voltage Low | VEXOVPL | 5.65 | 6 | 6.35 | V | | 11 |
| Switching Frequency | fSW | 2 | 2.2 | 2.4 | MHz | | 11 |
| Synchronization Frequency Range | fSW_EX | 1.8 | | 2.4 | MHz | External Clock Input | 11 |
| Switching Frequency (Spread Spectrum) | fSWSSR | 1.9 | | 2.52 | MHz | VSSCG = 5 V | 11 |
| High Side FET ON Resistance | RONH | | 210 | 440 | mΩ | VBST-VSW = 3.3 V | 11 |
| Low Side FET ON Resistance | RONL | | 140 | 290 | mΩ | VVCC_EX = 3.3 V | 11 |
| Over Current Protection Threshold | IOCP10 | 1 | 1.25 | 1.5 | A | VOCP_SEL = 5 V | 11 |
| Over Current Protection Threshold | IOCP05 | 0.5 | 0.625 | 0.75 | A | VOCP_SEL = 0 V | 11 |
| Output Voltage (BD9P135EFV-C), VOUT_SNS Voltage, PWM Mode | VOUT_SNS1 | 3.25 | 3.308 | 3.366 | V | VOUT_SNS Voltage, PWM Mode | 11 |
| Enter SLEEP State Voltage (BD9P135EFV-C) | VOUT_SNS2 | 3.275 | 3.349 | 3.424 | V | VOUT_SNS Rising, Light Load Mode | 11 |
| Exit SLEEP State Voltage (BD9P135EFV-C) | VOUT_SNS3 | 3.266 | 3.341 | 3.416 | V | VOUT_SNS Falling, Light Load Mode | 11 |
| Soft Start Time | tSS | 2.5 | 3 | 3.9 | ms | VFB1 x 0.1 to VFB1 x 0.9 | 11 |
| Reset Threshold Voltage Low (BD9P135EFV-C) | | 3 | 3.065 | 3.13 | V | VOUT_SNS Sweep Down | 12 |
| Reset Threshold Voltage High (BD9P135EFV-C) | | 3.08 | 3.16 | 3.24 | V | VOUT_SNS Sweep Up | 12 |
| Reset ON Resistance | RRST | | 190 | 400 | Ω | VIN = 2 V, VEN = 0 V, IRESET = 1 mA | 12 |
| Reset Active Time | tRSTNACT | 2 | 3.6 | 5 | ms | | 12 |
| VOUT_SNS OVP Threshold Voltage High (BD9P135EFV-C) | | 3.402 | 3.541 | 3.693 | V | | 12 |
| VOUT_SNS OVP Threshold Voltage Low (BD9P135EFV-C) | | 3.321 | 3.455 | 3.609 | V | | 12 |
| SCP Threshold Voltage High (BD9P135EFV-C) | | 2.81 | 2.97 | 3.14 | V | VOUT_SNS Sweep Up | 12 |
| SCP Threshold Voltage Low (BD9P135EFV-C) | | 2.48 | 2.64 | 2.81 | V | VOUT_SNS Sweep Down | 12 |
| Output Voltage for BD9P135EFV-C | VOUT | | 3.3 | | V | | 10 |
| Junction to Ambient (1s board) | θJA | | 143 | | °C/W | 1s board (JESD51-3) | 9 |
| Junction to Ambient (2s2p board) | θJA | | 26.8 | | °C/W | 2s2p board (JESD51-5, 7) | 9 |
| Junction to Top Characterization Parameter (1s board) | ΨJT | | 8 | | °C/W | 1s board (JESD51-3) | 9 |
| Junction to Top Characterization Parameter (2s2p board) | ΨJT | | 4 | | °C/W | 2s2p board (JESD51-5, 7) | 9 |
## Materials and finish
As the datasheet states them (page.json `metadata.appearance`; the 3D model's colours follow it).
| Part | Material | Colour / plating | Datasheet says | Page |
|---|---|---|---|---|
| housing | abs | | Human Body Model (HBM)(Note 1) VESD_HBM ±2 kV Caution 1: Operating the IC over the absolute maximum ratings may damage the IC. The damage can either be a short circuit between pins or an open circuit | 9 |
| contacts | copper | | 7. To minimize the emission noise from switching node, the distance between the SW pins to inductor should be as short as possible and not to expand the copper area more than necessary. | 49 |
## CAD (KiCad official)
- Symbol: `BD9P135EFV-CE2`
- Footprint: `Package_SO:TSSOP-20-1EP_4.4x6.5mm_P0.65mm_EP2.15x3.35mm`
- 3D model: HTSSOP-20-EP, generated from the KiCad footprint (body from the F.Fab outline, terminals on the pads, 1.2 mm nominal TSSOP height). Neither the vendor nor KiCad ships a 3D model for this package, so the dimensions are nominal, not the manufacturer's CAD (STEP)
- 3D model files: `bd9p135efv-ce2-etched.step` / `bd9p135efv-ce2-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `bd9p135efv-ce2.step` / `bd9p135efv-ce2.glb` are the bare package body.
## Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- **Datasheet:** [ROHM Semicon datasheet](docs/bd9p135efv-ce2-datasheet.pdf) (60 pp, sha256 `f5977b9e0766c210`, retrieved 2026-10-30, tier: manufacturer)
- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.3`, primary `claude-haiku-5-5` (text), consensus `claude-sonnet-5-5` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
- **CAD:** KiCad official libraries (CC-BY-SA 4.0).
[Datasheet PDF](docs/bd9p135efv-ce2-datasheet.pdf)