component

BD9G401EFJ-ME2

Public Made by Adom

by adom

ROHM DC-DC Converters, HTSOP-8-EP. Pinout extracted from the datasheet, KiCad symbol/footprint/3D.

componentpmicbd9g401efj-me2
Overview Files Discover Packages Releases Dependencies Issues Breadcrumbs Pull Requests Activity
main
Download ZIP Propose a change
Generated by kicad-footprint-generator · KiCad file format 20260206
Name Last commit message Last updated
docs bd9g401efj-me2: re-etch, flat white mark read from pin 1 (service-occt 1.4.0) + chip hero · Ray 1mo ago
viewers bd9g401efj-me2: viewers · Ray 2mo ago
bd9g401efj-me2-etched.fit.json bd9g401efj-me2: re-etch, flat white mark read from pin 1 (service-occt 1.4.0) + chip hero · Ray 1mo ago
bd9g401efj-me2-etched.glb bd9g401efj-me2: re-etch, flat white mark read from pin 1 (service-occt 1.4.0) + chip hero · Ray 1mo ago
bd9g401efj-me2-etched.step bd9g401efj-me2: re-etch, flat white mark read from pin 1 (service-occt 1.4.0) + chip hero · Ray 1mo ago
bd9g401efj-me2.glb Publish 0.1.0 · Ray 2mo ago
bd9g401efj-me2.kicad_mod Publish 0.1.0 · Ray 2mo ago
bd9g401efj-me2.kicad_sym Publish 0.1.0 · Ray 2mo ago
bd9g401efj-me2.lbr Publish 0.1.0 · Ray 2mo ago
bd9g401efj-me2.step Publish 0.1.0 · Ray 2mo ago
package.json Publish 0.2.0 · Ray 2mo ago
page.json bd9g401efj-me2: specified limits as data (metadata.characteristics, 39 rows from the datasheet) · Ray 23d ago
README.md bd9g401efj-me2: specified limits as data (metadata.characteristics, 39 rows from the datasheet) · Ray 23d ago

BD9G401EFJ-ME2

ROHM · DC-DC Converters · HTSOP-8-EP

BD9G401EFJ-ME2 from ROHM, in a HTSOP-8-EP. Pinout and pin descriptions extracted from the manufacturer datasheet by ds2sf; symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 LX output Switching node. Drain of the internal high-side N-channel power MOSFET (RonH = 140 mΩ typ); connect the external inductor and catch diode here. Absolute max LX-GND = 45 V.
2 GND power_in Device ground return for the power stage and control logic. Also serves as the reference for all pin voltage limits.
3 VC output Error amplifier output / compensation node. Connect an external RC network to GND to set the loop compensation. Absolute max VC-GND = 7 V.
4 FB input Feedback input to the error amplifier. Internal reference is 0.8 V (typ); connect a resistor divider from VOUT to set the output voltage. Absolute max FB-GND = 7 V.
5 SYNC input External clock synchronization input, 250 kHz to 500 kHz. VIH ≥ 2.0 V, VIL ≤ 0.8 V; internally pulled down. Tie to GND when the synchronization function is not used. Absolute max SYNC-GND = 7 V.
6 EN input Enable / on-off input. VEN < 0.3 V = IC off; 0.3-1.4 V turns internal REG on; > 1.8 V (typ) enables the IC with 10 µA (typ) source current hysteresis. May be driven from a resistor divider off VCC for arbitrary UVLO. Absolute max EN-GND = 45 V.
7 BST passive Bootstrap capacitor terminal for the high-side FET gate drive. Connect a 0.1 µF capacitor from BST to LX. Absolute max BST-GND = 50 V, BST-LX = 7 V.
8 VCC power_in Input supply pin, 4.5 V to 42 V operating (4.65 V required for start-up). Bypass with a 10 µF / 50 V ceramic close to the pin. Absolute max VCC-GND = 45 V.
9 THERMAL_PAD passive Exposed thermal pad on the package underside. Must always be connected to GND and to a copper heat-spreading area/thermal vias for heat dissipation.

Key specifications

Parameter Value
Manufacturer ROHM
Package HTSOP-8-EP
Category PMIC
Pins 9

Ordering variants

  • BD9G401EFJ-ME2

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
VCC Standby Current Ist 0 10 µA VEN= 0V 6
VCC Circuit Current Icc 1.2 2.4 mA VFB= 1.2V 6
UVLO Detect Voltage Vuv 3.65 4 4.35 V VCC down sweep 6
UVLO Hysteresis Width Vuvhy 50 200 300 mV 6
Oscillator Frequency fosc 270 300 330 kHz 6
MaxDuty Cycle Dmax 95 97 99.9 % VSYNC= 0V 6
FB Threshold Voltage (Ta= 25°C) VFB 0.788 0.8 0.812 V Ta= 25°C 6
FB Threshold Voltage (Ta= -40 to +105°C) VFBT 0.784 0.8 0.816 V Ta= -40 to +105°C 6
FB Input Bias Current IFB -1 0 1 µA VFB= 3.0V 6
FB Leak Current Ileak -1 0 1 µA VFB= 0V 6
SoftStart Time tsoft 5.6 8 10.4 ms VSYNC= 0V 6
Over Current Detect Iocp 4 6 A 6
EN Terminal Internal REG ON-Voltage VENON 0.3 1.4 V 6
EN Terminal IC Output on Threshold VENUV 1.65 1.8 1.95 V IC on or off threshold 6
EN Terminal Source Current IEN 9 10 11 µA VEN= 3V 6
SYNC Terminal Control Voltage High VSYNCH 2 5.5 V 6
SYNC Terminal Control Voltage Low VSYNCL -0.3 0.8 V 6
SYNC Terminal Input Current ISYNC 6 12 24 µA VSYNC= 3V 6
Power Supply Voltage (recommended) VCC 4.5 42 V 5
Output Voltage (recommended) VOUT 0.8 V 5
Output Current (recommended) IOUT 3.5 A 5
SYNC Terminal Input Frequency fSYNC 250 500 kHz 5
Input Capacitance CIN 2.2 µF 5
Inductance L 11 µH 5
VCC-GND Voltage VCC 45 V 4
BST-GND Voltage VBST 50 V 4
BST-LX Voltage VBST-LX 7 V 4
EN-GND Voltage VEN 45 V 4
LX-GND Voltage VLX 45 V 4
FB-GND Voltage VFB 7 V 4
VC-GND Voltage VVC 7 V 4
SYNC-GND Voltage VSYNC 7 V 4
Operating Temperature Topr -40 105 °C 4
Storage Temperature Tstg -55 150 °C 4
Junction Temperature Tjmax 150 °C 4
Junction to Ambient Thermal Resistance θJA 206.4 °C/W 1s(Note 3) 4
Junction to Ambient Thermal Resistance θJA 45.2 °C/W 2s2p(Note 4) 4
Junction to Top Characterization Parameter ΨJT 21 °C/W 1s(Note 3) 4
Junction to Top Characterization Parameter ΨJT 13 °C/W 2s2p(Note 4) 4

CAD (KiCad official)

  • Symbol: BD9G401EFJ-ME2
  • Footprint: Package_SO:HTSOP-8-1EP_3.9x4.9mm_P1.27mm_EP2.4x3.2mm
  • 3D model: HTSOP-8-EP (KiCad packages3D, STEP)
  • 3D model files: bd9g401efj-me2-etched.step / bd9g401efj-me2-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); bd9g401efj-me2.step / bd9g401efj-me2.glb are the bare package body.

3D model downloads

Two STEP files. Same geometry, different body top:

File Size Use it when
bd9g401efj-me2.step 127 KB You want the bare part, or you mark your own boards.
bd9g401efj-me2-etched.step 2.5 MB You want the part with BD9G401EFJ-ME2 already on it.

The marking in the etched file is real recessed geometry cut into the solid, not a texture or a decal: 629 faces against 152 in the bare model. It survives export, section views, and rendering in any CAD tool, and it drops straight into KiCad or Fusion with no extra setup.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: ROHM datasheet (31 pp, sha256 2dfe5ab3693fd35c, retrieved 2026-08-17, tier: manufacturer)
  • Extractor: ds2sf (Claude). Every pin and dimension is cited to a datasheet page; it refuses to fabricate.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF