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Set visibility: public

Ray ·7d80234d52 ·2mo ago ·parent 8aeee62
1 file changed +9−6
page.json+9−6
@@ -32,7 +32,7 @@         "number": "1",         "name": "LX",         "type": "output",-        "description": "Switching node. Drain of the internal high-side N-channel power MOSFET (RonH = 140 m\u03a9 typ); connect the external inductor and catch diode here. Absolute max LX-GND = 45 V."+        "description": "Switching node. Drain of the internal high-side N-channel power MOSFET (RonH = 140 mΩ typ); connect the external inductor and catch diode here. Absolute max LX-GND = 45 V."       },       {         "number": "2",@@ -56,25 +56,25 @@         "number": "5",         "name": "SYNC",         "type": "input",-        "description": "External clock synchronization input, 250 kHz to 500 kHz. VIH \u2265 2.0 V, VIL \u2264 0.8 V; internally pulled down. Tie to GND when the synchronization function is not used. Absolute max SYNC-GND = 7 V."+        "description": "External clock synchronization input, 250 kHz to 500 kHz. VIH ≥ 2.0 V, VIL ≤ 0.8 V; internally pulled down. Tie to GND when the synchronization function is not used. Absolute max SYNC-GND = 7 V."       },       {         "number": "6",         "name": "EN",         "type": "input",-        "description": "Enable / on-off input. VEN < 0.3 V = IC off; 0.3-1.4 V turns internal REG on; > 1.8 V (typ) enables the IC with 10 \u00b5A (typ) source current hysteresis. May be driven from a resistor divider off VCC for arbitrary UVLO. Absolute max EN-GND = 45 V."+        "description": "Enable / on-off input. VEN < 0.3 V = IC off; 0.3-1.4 V turns internal REG on; > 1.8 V (typ) enables the IC with 10 µA (typ) source current hysteresis. May be driven from a resistor divider off VCC for arbitrary UVLO. Absolute max EN-GND = 45 V."       },       {         "number": "7",         "name": "BST",         "type": "passive",-        "description": "Bootstrap capacitor terminal for the high-side FET gate drive. Connect a 0.1 \u00b5F capacitor from BST to LX. Absolute max BST-GND = 50 V, BST-LX = 7 V."+        "description": "Bootstrap capacitor terminal for the high-side FET gate drive. Connect a 0.1 µF capacitor from BST to LX. Absolute max BST-GND = 50 V, BST-LX = 7 V."       },       {         "number": "8",         "name": "VCC",         "type": "power_in",-        "description": "Input supply pin, 4.5 V to 42 V operating (4.65 V required for start-up). Bypass with a 10 \u00b5F / 50 V ceramic close to the pin. Absolute max VCC-GND = 45 V."+        "description": "Input supply pin, 4.5 V to 42 V operating (4.65 V required for start-up). Bypass with a 10 µF / 50 V ceramic close to the pin. Absolute max VCC-GND = 45 V."       },       {         "number": "9",@@ -144,5 +144,8 @@     "docs/bd9g401efj-me2-datasheet.pdf",     "viewers/symbol.html",     "viewers/footprint.html"-  ]+  ],+  "visibility": {+    "public": true+  } }\ No newline at end of file