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BD9B400MUV-E2

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ROHM DC-DC Converters, VQFN-16-EP(3x3). Pinout extracted from the datasheet, KiCad symbol/footprint/3D.

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docs bd9b400muv-e2: re-etch, flat white mark read from pin 1 (service-occt 1.4.0) + chip hero · Ray 1mo ago
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bd9b400muv-e2-etched.fit.json bd9b400muv-e2: re-etch, flat white mark read from pin 1 (service-occt 1.4.0) + chip hero · Ray 1mo ago
bd9b400muv-e2-etched.glb bd9b400muv-e2: re-etch, flat white mark read from pin 1 (service-occt 1.4.0) + chip hero · Ray 1mo ago
bd9b400muv-e2-etched.step bd9b400muv-e2: re-etch, flat white mark read from pin 1 (service-occt 1.4.0) + chip hero · Ray 1mo ago
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page.json bd9b400muv-e2: specified limits as data (metadata.characteristics, 43 rows from the datasheet) · Ray 23d ago
README.md bd9b400muv-e2: specified limits as data (metadata.characteristics, 43 rows from the datasheet) · Ray 23d ago

BD9B400MUV-E2

ROHM · DC-DC Converters · VQFN-16-EP(3x3)

BD9B400MUV-E2 from ROHM, in a VQFN-16-EP(3x3). Pinout and pin descriptions extracted from the manufacturer datasheet by ds2sf; symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 PVIN power_in Power supply input to the switching regulator output stage (2.7 V to 5.5 V). Tied in parallel with pin 2. Requires a 22µF ceramic bypass capacitor.
2 PVIN power_in Power supply input to the switching regulator output stage (2.7 V to 5.5 V). Tied in parallel with pin 1.
3 PGND power_in Power ground for the switching regulator output stage. Tied in parallel with pin 4.
4 PGND power_in Power ground for the switching regulator output stage. Tied in parallel with pin 3.
5 AGND power_in Analog ground for the control circuit. Kelvin-connect to PGND at a single point.
6 FB input Feedback input, the inverting input to the error amplifier and main comparator. Regulates to VFB = 0.8 V (typ, 0.792-0.808 V) via an external resistor divider from VOUT.
7 FREQ input Switching-frequency select. Tie to GND for constant on-time corresponding to 2 MHz; tie to AVIN for 1 MHz. Must be fixed to AVIN or ground in operation.
8 MODE input Switching-control mode select. Tie to AVIN for fixed-frequency PWM; tie to GND to enable Deep-SLLM auto mode (auto switching between Deep-SLLM and fixed PWM). Must be fixed to AVIN or ground in operation.
9 SS passive Soft-start timing. Connect a capacitor to GND to set the output-voltage rise time; internal soft-start current ISS ≈ 1 µA (typ). Internal soft-start defaults to 1 ms (typ) when SS is open.
10 SW power_out Switch node - source of the high-side MOSFET and drain of the low-side MOSFET. Pins 10, 11, 12 are internally connected; connect the output inductor here (0.47µH-1µH for FREQ=L, 1µH-1.5µH for FREQ=H).
11 SW power_out Switch node (paralleled with pins 10 and 12).
12 SW power_out Switch node (paralleled with pins 10 and 11). A 0.1µF bootstrap capacitor between SW and BOOT is required.
13 BOOT passive Bootstrap capacitor node for the high-side MOSFET gate drive. Connect a 0.1µF ceramic capacitor between BOOT and SW; V(BOOT-SW) is the high-side gate-drive supply (~5 V).
14 PGD output Power-Good open-drain output. Requires an external pull-up resistor. Goes high-Z (High) when VFB exceeds 80% of 0.8 V; RPGD ≈ 100 Ω (typ), max sink 1 mA gives VOL ≈ 0.1 V.
15 EN input Enable input. Drive Low (≤0.8 V) to enter shutdown; drive High (≥2.0 V) to enable the device. IEN ≈ 5 µA @ EN=5V. Must be terminated (no internal pull).
16 AVIN power_in Analog/control-circuit supply (2.7 V to 5.5 V). Must be connected to PVIN. A 0.1µF ceramic bypass capacitor is recommended.
17 E-Pad power_in Backside exposed thermal pad. Connect to the internal PCB ground plane with multiple thermal vias for heat dissipation.

Key specifications

Parameter Value
Manufacturer ROHM
Package VQFN-16-EP(3x3)
Category PMIC
Pins 17

Ordering variants

Same part, different packaging or reel option.

  • BD9B400MUV-E2

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
Supply Voltage VPVIN, VAVIN -0.3 7 V 5
EN Terminal Voltage VEN -0.3 7 V 5
MODE Terminal Voltage VMODE -0.3 7 V 5
FREQ Terminal Voltage VFREQ -0.3 7 V 5
PGD Terminal Voltage VPGD -0.3 7 V 5
Voltage from GND to BOOT VBOOT -0.3 14 V 5
Voltage from SW to BOOT ΔVBOOT -0.3 7 V 5
FB Terminal Voltage VFB -0.3 7 V 5
Output Current IOUT 4.5 A 5
Operating Temperature Range Topr -40 85 °C 5
Storage Temperature Range Tstg -55 150 °C 5
Supply Voltage VPVIN, VAVIN 2.7 5.5 V Ta= -40°C to +85°C 5
Output Current IOUT 4 A Ta= -40°C to +85°C; Pd, ASO should not be exceeded 5
Output Voltage Range VRANGE 0.8 V Ta= -40°C to +85°C; max printed as VPVIN × 0.8 5
Standby Supply Current ISTB 0 10 µA EN=GND 6
Operating Supply Current ICC 45 80 µA FREQ=AVIN, IOUT=0mA, Non switching 6
UVLO Detection Threshold VUVLO1 2.35 2.45 2.55 V VIN falling 6
UVLO Release Threshold VUVLO2 2.425 2.55 2.7 V VIN rising 6
UVLO Hysteresis VUVLOHYS 50 100 200 mV 6
EN Input High Level Voltage VENH 2 V 6
EN Input Low Level Voltage VENL 0.8 V 6
EN Input Current IEN 5 10 µA EN=5V 6
FB Terminal Voltage VFB 0.792 0.8 0.808 V 6
FB Input Bias Current IFB 1 µA FB=0.8V 6
Internal Soft Start Time TSS 0.5 1 2 ms SS terminal is open 6
Soft Start Terminal Current ISS 0.5 1 2 µA 6
FREQ Input Low Level Voltage VFRQL 0.3 V 6
MODE Input Low Level Voltage VMODEL 0.3 V 6
On time1 ONT1 96 120 144 ns VOUT=1.2V, FREQ=GND 6
On time2 ONT2 192 240 288 ns VOUT=1.2V, FREQ=AVIN 6
Power Good Rising Threshold VPGDH 75 80 85 % FB rising, VPGDH=FB/VFBx100 6
Power Good Falling Threshold VPGDL 65 70 75 % FB falling, VPGDL=FB/VFBx100 6
Output Leakage Current ILKPGD 0 5 µA PGD=5V 6
Power Good On Resistance RPGD 100 200 Ω 6
Power Good Low Level Voltage PGDVL 0.1 0.2 V IPGD=1mA 6
High Side FET On Resistance RONH 30 60 mΩ BOOT - SW = 5 V 6
Low Side FET On Resistance RONL 30 60 mΩ 6
High Side Output Leakage Current RILH 0 10 µA No switching 6
Low Side Output Leakage Current RILL 0 10 µA No switching 6
Thermal Resistance Junction to Ambient (1s board) θJA 189 °C/W 1s(Note 3), JESD51-2A still air, JESD51-3 board 5
Thermal Resistance Junction to Ambient (2s2p board) θJA 57.5 °C/W 2s2p(Note 4), JESD51-2A still air, JESD51-5,7 board 5
Junction to Top Characterization Parameter (1s board) ΨJT 23 °C/W 1s(Note 3) 5
Junction to Top Characterization Parameter (2s2p board) ΨJT 10 °C/W 2s2p(Note 4) 5

CAD (KiCad official)

  • Symbol: BD9B400MUV-E2
  • Footprint: Package_DFN_QFN:QFN-16-1EP_3x3mm_P0.5mm_EP1.7x1.7mm
  • 3D model: VQFN-16-EP(3x3) (KiCad packages3D, STEP)
  • 3D model files: bd9b400muv-e2-etched.step / bd9b400muv-e2-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); bd9b400muv-e2.step / bd9b400muv-e2.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: ROHM datasheet (33 pp, sha256 775e756d99121154, retrieved 2026-08-17, tier: lcsc)
  • Extractor: ds2sf (Claude). Every pin and dimension is cited to a datasheet page; it refuses to fabricate.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF