component
BD9611MUV-E2
Public Made by Adomby adom
ROHM Semicon DC-DC Converters, VQFN-20-EP(4x4). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
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BD9611MUV-E2
ROHM Semicon · DC-DC Converters · VQFN-20-EP(4x4)
BD9611MUV-E2 from ROHM Semicon, in a VQFN-20-EP(4x4). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | GND | power_in | Ground pin. |
| 2 | SS | passive | Programmable soft-start pin; capacitor charged by 1uA internal source, soft-start time tss = (CSS×0.8V)/1uA. |
| 3 | INV | input | Inverting input to the error amplifier, compared to the 0.8V (±1%) reference, with compensation connected between INV and FB. |
| 4 | FB | output | Output of the error amplifier, used as the PWM control signal with phase compensation connected to INV. |
| 5 | RCL | passive | Programmable current limit setting; the RCL resistor sets the CLH-CLL over-current threshold. |
| 6 | RT | passive | Programmable frequency setting; resistor to GND sets oscillator frequency in the 50kHz to 500kHz range, FOSC = 15900 × RRT^-0.955 kHz. |
| 7 | RTSS | passive | Reference voltage pin for RT (0.5V buffered), with a 0.01uF capacitor to ground recommended. |
| 8 | CLKOUT | output | Internal clock pulse output, a square wave synchronized to the oscillator for master-slave synchronization. |
| 9 | PGND | power_in | Power ground pin. |
| 10 | SYNC | input | Synchronization input accepting external clock of 50 to 500kHz (±10% of free-run), high level 2.8V to 5.0V, pulse width over 500ns; connect to GND when not configured as slave. |
| 11 | LG | output | Gate driver output for the external low-side N-channel FET. |
| 12 | REG10 | power_out | Output of the 10V internal regulator (9 to 11V) supplying the low-side driver; needs a 1.0uF ceramic capacitor to GND and limits current to 20mA when shorted to GND. |
| 13 | LX | passive | Connects to the switching node of the converter. |
| 14 | HG | output | Gate driver output for the external high-side N-channel FET. |
| 15 | BST | power_in | Gate drive voltage input for the high-side N-channel FET, charged from REG10 through an internal switch with a capacitor to LX. |
| 16 | CLL | input | Inverting input to the current detector for high-side current sensing (CLH-CLL). |
| 17 | CLH | input | Input to the current detector for high-side current sensing (CLH-CLL). |
| 18 | VCC | power_in | Power supply input, 10V to 56V. |
| 19 | CTL | input | Shutdown/enable pin: IC turns off below 0.3V, regulators on above 2.4V, DRV on above 2.8V, EXUVLO threshold 2.6V (±3%) with 20uA (±25%) current source, clamped at 5.6V through 100kΩ. |
| 20 | REG5 | power_out | Output of the 5V (±2%) internal regulator, usable externally up to 2mA max with a 0.1uF ceramic capacitor to GND. |
| 21 | EP | passive | Thermal pad; connecting it to GND is recommended to improve thermal dissipation. |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | ROHM Semicon |
| Package | VQFN-20-EP(4x4) |
| Category | Power Management ICs |
| Pins | 21 |
Electrical characteristics
Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Oscillator frequency | FOSC | 93 | 100 | 107 | kHz | RT=200kΩ | 6 |
| RTSS maximum current (sink/source) | IRTSS | 2.5 | 5 | 10 | uA | VRTSS=0V/1.0V | 6 |
| RTSS pre-charge threshold | VRTSSTH | 0.45 | 0.5 | 0.55 | V | 6 | |
| RTSS pre-charge current | IRTSSP | 50 | 100 | 200 | uA | VRTSS=0.3V | 6 |
| SS source current | ISSSO | 0.7 | 1 | 1.3 | uA | SS=1.0V | 6 |
| UVLO threshold (VCC) | VUTHVCC | 8.5 | 9 | 9.5 | V | VCC rise-up | 6 |
| UVLO threshold (REG10) | VUTHR10 | 7.9 | 8.7 | 9.5 | V | REG10 rise-up | 6 |
| UVLO threshold (REG5) | VUTHR5 | 4.2 | 4.5 | 4.8 | V | REG5 rise-up | 6 |
| UVLO hysteresis (VCC) | VUHSVCC | 0.5 | 1 | V | VCC pin | 6 | |
| UVLO hysteresis (REG10) | VUHSR10 | 0.5 | 1 | V | REG10 pin | 6 | |
| UVLO hysteresis (REG5) | VUHSR5 | 0.2 | 0.4 | V | REG5 pin | 6 | |
| UVLO threshold (CTL) | VEXUTH | 2.522 | 2.6 | 2.678 | V | CTL rise-up | 6 |
| UVLO hysteresis current | IUVHYS | -25 | -20 | -15 | uA | CTL=5V | 6 |
| Reference voltage | VNON | 0.792 | 0.8 | 0.808 | V | INV=FB | 6 |
| INV input bias current | IBINV | 0.01 | 1 | uA | INV=0.8V | 6 | |
| FB min voltage | VFBL | 0 | 0.5 | V | 6 | ||
| FB sink current | IFBSI | 0.5 | 2 | mA | FB=1.25V, INV=1.5V | 6 | |
| FB source current | IFBSO | 60 | 120 | uA | FB=1.25V, INV=0V | 6 | |
| PWM input threshold voltage | VT0 | 1.4 | 1.5 | 1.6 | V | 0% Duty, FB pin vol. | 6 |
| HG min OFF pulse width | HGMIN | 150 | 350 | 450 | ns | FB=3V | 6 |
| Output driver PchFET Ron | RONH | 6 | 10 | Ω | Iout=0.1A | 6 | |
| Output driver NchFET Ron | RONL | 1 | 3 | Ω | Iout=0.1A | 6 | |
| OCP threshold voltage | VOCPTH | 160 | 200 | 240 | mV | Between CLH and CLL (RCL=7.5kΩ) | 7 |
| OCP propagation delay to output | TOCP | 200 | 300 | ns | 7 | ||
| REG10 output voltage | VREG10 | 9 | 10 | 11 | V | 7 | |
| REG5 output voltage | VREG5 | 4.9 | 5 | 5.1 | V | 7 | |
| REG5 current ability | IREG5 | 10 | 30 | mA | V=VREG5×0.95 | 7 | |
| SYNC input current | ISYNC | 8 | 16 | uA | SYNC=5V | 7 | |
| SYNC input voltage H | VSYNCH | 2.8 | 5 | V | 7 | ||
| SYNC input voltage L | VSYNCL | 0.3 | V | 7 | |||
| CLKOUT sink current | ICLKSI | 1.5 | 3 | mA | CLKOUT=0.5V | 7 | |
| CLKOUT source current | ICLKSO | 1.5 | 3 | mA | CLKOUT=4.5V | 7 | |
| CTL output current | ICTL | 15 | 20 | 25 | uA | CTL=5V | 7 |
| CTL input voltage L | VCTLL | 0.3 | V | 7 | |||
| CTL input voltage1 H | VCTL1H | 2.2 | 2.4 | V | REG5, REG10 start up | 7 | |
| CTL input voltage2 H | VCTL2H | 2.8 | V | DRV start up | 7 | ||
| Stand-by current | ISC | 0 | 5 | uA | CTL=0V | 7 | |
| Quiescent current | ICC | 1 | 2 | 4 | mA | INV=5V | 7 |
| Supply voltage | VCC | 60 | V | 5 | |||
| BST pin voltage | VBST | 70 | V | 5 | |||
| Between BST pin and LX pin | VBSTLX | 15 | V | 5 | |||
| REG10 pin voltage | VREG10 | 15 | V | 5 | |||
| REG5 pin voltage | VREG5 | 7 | V | 5 | |||
| SYNC pin voltage | VSYNC | 7 | V | 5 | |||
| Power dissipation | PD | 3.56 | W | 70×70×1.6 mm 4-layer board (Copper area: 70mm×70mm); reduced by 28.5mW for every 1°C above 25°C | 5 | ||
| Operating temperature range | TOPR | -40 | 105 | °C | 5 | ||
| Storage temperature range | TSTG | -55 | 150 | °C | 5 | ||
| Junction temperature | TJMAX | 150 | °C | 5 | |||
| Power supply voltage | VCC | 10 | 56 | V | 5 | ||
| Configurable output voltage | VOUT | 1 | V | upper limit printed as Vin×0.8V | 5 | ||
| Frequency | FOSC | 50 | 500 | kHz | 5 | ||
| RT resistor | RRT | 33 | 470 | kΩ | 5 | ||
| RTSS capacitor | CRTSS | 0.01 | 1 | uF | 5 | ||
| SYNC input duty | SYNCDTY | 40 | 60 | % | 5 | ||
| OCP program resistor | RRCL | 3.3 | 20 | kΩ | 5 | ||
| OCP counts to hiccup | NOCP | 2 | counts | In series or in every other cycle | 7 | ||
| OCP shut-down hold cycles | THICCUP | 32768 | cycles | T=1/FOSC, Hold time=T×THICCUP | 7 |
CAD (KiCad official)
- Symbol:
BD9611MUV-E2 - Footprint:
Package_DFN_QFN:QFN-20-1EP_4x4mm_P0.5mm_EP2.5x2.5mm - 3D model: VQFN-20-EP(4x4) (KiCad packages3D, STEP)
- 3D model files:
bd9611muv-e2-etched.step/bd9611muv-e2-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);bd9611muv-e2.step/bd9611muv-e2.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: ROHM Semicon datasheet (40 pp, sha256
f372809f61f7b81d, retrieved 2026-10-31, tier: manufacturer) - Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-sonnet-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).
# BD9611MUV-E2
**ROHM Semicon** · DC-DC Converters · VQFN-20-EP(4x4)
BD9611MUV-E2 from ROHM Semicon, in a VQFN-20-EP(4x4). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
## Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | GND | power_in | Ground pin. |
| 2 | SS | passive | Programmable soft-start pin; capacitor charged by 1uA internal source, soft-start time tss = (CSS×0.8V)/1uA. |
| 3 | INV | input | Inverting input to the error amplifier, compared to the 0.8V (±1%) reference, with compensation connected between INV and FB. |
| 4 | FB | output | Output of the error amplifier, used as the PWM control signal with phase compensation connected to INV. |
| 5 | RCL | passive | Programmable current limit setting; the RCL resistor sets the CLH-CLL over-current threshold. |
| 6 | RT | passive | Programmable frequency setting; resistor to GND sets oscillator frequency in the 50kHz to 500kHz range, FOSC = 15900 × RRT^-0.955 kHz. |
| 7 | RTSS | passive | Reference voltage pin for RT (0.5V buffered), with a 0.01uF capacitor to ground recommended. |
| 8 | CLKOUT | output | Internal clock pulse output, a square wave synchronized to the oscillator for master-slave synchronization. |
| 9 | PGND | power_in | Power ground pin. |
| 10 | SYNC | input | Synchronization input accepting external clock of 50 to 500kHz (±10% of free-run), high level 2.8V to 5.0V, pulse width over 500ns; connect to GND when not configured as slave. |
| 11 | LG | output | Gate driver output for the external low-side N-channel FET. |
| 12 | REG10 | power_out | Output of the 10V internal regulator (9 to 11V) supplying the low-side driver; needs a 1.0uF ceramic capacitor to GND and limits current to 20mA when shorted to GND. |
| 13 | LX | passive | Connects to the switching node of the converter. |
| 14 | HG | output | Gate driver output for the external high-side N-channel FET. |
| 15 | BST | power_in | Gate drive voltage input for the high-side N-channel FET, charged from REG10 through an internal switch with a capacitor to LX. |
| 16 | CLL | input | Inverting input to the current detector for high-side current sensing (CLH-CLL). |
| 17 | CLH | input | Input to the current detector for high-side current sensing (CLH-CLL). |
| 18 | VCC | power_in | Power supply input, 10V to 56V. |
| 19 | CTL | input | Shutdown/enable pin: IC turns off below 0.3V, regulators on above 2.4V, DRV on above 2.8V, EXUVLO threshold 2.6V (±3%) with 20uA (±25%) current source, clamped at 5.6V through 100kΩ. |
| 20 | REG5 | power_out | Output of the 5V (±2%) internal regulator, usable externally up to 2mA max with a 0.1uF ceramic capacitor to GND. |
| 21 | EP | passive | Thermal pad; connecting it to GND is recommended to improve thermal dissipation. |
## Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | ROHM Semicon |
| Package | VQFN-20-EP(4x4) |
| Category | Power Management ICs |
| Pins | 21 |
## Electrical characteristics
Limits as printed in the datasheet (page.json `metadata.characteristics` carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Oscillator frequency | FOSC | 93 | 100 | 107 | kHz | RT=200kΩ | 6 |
| RTSS maximum current (sink/source) | IRTSS | 2.5 | 5 | 10 | uA | VRTSS=0V/1.0V | 6 |
| RTSS pre-charge threshold | VRTSSTH | 0.45 | 0.5 | 0.55 | V | | 6 |
| RTSS pre-charge current | IRTSSP | 50 | 100 | 200 | uA | VRTSS=0.3V | 6 |
| SS source current | ISSSO | 0.7 | 1 | 1.3 | uA | SS=1.0V | 6 |
| UVLO threshold (VCC) | VUTHVCC | 8.5 | 9 | 9.5 | V | VCC rise-up | 6 |
| UVLO threshold (REG10) | VUTHR10 | 7.9 | 8.7 | 9.5 | V | REG10 rise-up | 6 |
| UVLO threshold (REG5) | VUTHR5 | 4.2 | 4.5 | 4.8 | V | REG5 rise-up | 6 |
| UVLO hysteresis (VCC) | VUHSVCC | | 0.5 | 1 | V | VCC pin | 6 |
| UVLO hysteresis (REG10) | VUHSR10 | | 0.5 | 1 | V | REG10 pin | 6 |
| UVLO hysteresis (REG5) | VUHSR5 | | 0.2 | 0.4 | V | REG5 pin | 6 |
| UVLO threshold (CTL) | VEXUTH | 2.522 | 2.6 | 2.678 | V | CTL rise-up | 6 |
| UVLO hysteresis current | IUVHYS | -25 | -20 | -15 | uA | CTL=5V | 6 |
| Reference voltage | VNON | 0.792 | 0.8 | 0.808 | V | INV=FB | 6 |
| INV input bias current | IBINV | | 0.01 | 1 | uA | INV=0.8V | 6 |
| FB min voltage | VFBL | | 0 | 0.5 | V | | 6 |
| FB sink current | IFBSI | 0.5 | 2 | | mA | FB=1.25V, INV=1.5V | 6 |
| FB source current | IFBSO | 60 | 120 | | uA | FB=1.25V, INV=0V | 6 |
| PWM input threshold voltage | VT0 | 1.4 | 1.5 | 1.6 | V | 0% Duty, FB pin vol. | 6 |
| HG min OFF pulse width | HGMIN | 150 | 350 | 450 | ns | FB=3V | 6 |
| Output driver PchFET Ron | RONH | | 6 | 10 | Ω | Iout=0.1A | 6 |
| Output driver NchFET Ron | RONL | | 1 | 3 | Ω | Iout=0.1A | 6 |
| OCP threshold voltage | VOCPTH | 160 | 200 | 240 | mV | Between CLH and CLL (RCL=7.5kΩ) | 7 |
| OCP propagation delay to output | TOCP | | 200 | 300 | ns | | 7 |
| REG10 output voltage | VREG10 | 9 | 10 | 11 | V | | 7 |
| REG5 output voltage | VREG5 | 4.9 | 5 | 5.1 | V | | 7 |
| REG5 current ability | IREG5 | 10 | 30 | | mA | V=VREG5×0.95 | 7 |
| SYNC input current | ISYNC | | 8 | 16 | uA | SYNC=5V | 7 |
| SYNC input voltage H | VSYNCH | 2.8 | | 5 | V | | 7 |
| SYNC input voltage L | VSYNCL | | | 0.3 | V | | 7 |
| CLKOUT sink current | ICLKSI | 1.5 | 3 | | mA | CLKOUT=0.5V | 7 |
| CLKOUT source current | ICLKSO | 1.5 | 3 | | mA | CLKOUT=4.5V | 7 |
| CTL output current | ICTL | 15 | 20 | 25 | uA | CTL=5V | 7 |
| CTL input voltage L | VCTLL | | | 0.3 | V | | 7 |
| CTL input voltage1 H | VCTL1H | 2.2 | | 2.4 | V | REG5, REG10 start up | 7 |
| CTL input voltage2 H | VCTL2H | 2.8 | | | V | DRV start up | 7 |
| Stand-by current | ISC | | 0 | 5 | uA | CTL=0V | 7 |
| Quiescent current | ICC | 1 | 2 | 4 | mA | INV=5V | 7 |
| Supply voltage | VCC | | | 60 | V | | 5 |
| BST pin voltage | VBST | | | 70 | V | | 5 |
| Between BST pin and LX pin | VBSTLX | | | 15 | V | | 5 |
| REG10 pin voltage | VREG10 | | | 15 | V | | 5 |
| REG5 pin voltage | VREG5 | | | 7 | V | | 5 |
| SYNC pin voltage | VSYNC | | | 7 | V | | 5 |
| Power dissipation | PD | | | 3.56 | W | 70×70×1.6 mm 4-layer board (Copper area: 70mm×70mm); reduced by 28.5mW for every 1°C above 25°C | 5 |
| Operating temperature range | TOPR | -40 | | 105 | °C | | 5 |
| Storage temperature range | TSTG | -55 | | 150 | °C | | 5 |
| Junction temperature | TJMAX | | | 150 | °C | | 5 |
| Power supply voltage | VCC | 10 | | 56 | V | | 5 |
| Configurable output voltage | VOUT | 1 | | | V | upper limit printed as Vin×0.8V | 5 |
| Frequency | FOSC | 50 | | 500 | kHz | | 5 |
| RT resistor | RRT | 33 | | 470 | kΩ | | 5 |
| RTSS capacitor | CRTSS | 0.01 | | 1 | uF | | 5 |
| SYNC input duty | SYNCDTY | 40 | | 60 | % | | 5 |
| OCP program resistor | RRCL | 3.3 | | 20 | kΩ | | 5 |
| OCP counts to hiccup | NOCP | | 2 | | counts | In series or in every other cycle | 7 |
| OCP shut-down hold cycles | THICCUP | | 32768 | | cycles | T=1/FOSC, Hold time=T×THICCUP | 7 |
## CAD (KiCad official)
- Symbol: `BD9611MUV-E2`
- Footprint: `Package_DFN_QFN:QFN-20-1EP_4x4mm_P0.5mm_EP2.5x2.5mm`
- 3D model: VQFN-20-EP(4x4) (KiCad packages3D, STEP)
- 3D model files: `bd9611muv-e2-etched.step` / `bd9611muv-e2-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `bd9611muv-e2.step` / `bd9611muv-e2.glb` are the bare package body.
## Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- **Datasheet:** [ROHM Semicon datasheet](docs/bd9611muv-e2-datasheet.pdf) (40 pp, sha256 `f372809f61f7b81d`, retrieved 2026-10-31, tier: manufacturer)
- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.3`, primary `claude-sonnet-5-5` (text), consensus `claude-sonnet-5-5` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
- **CAD:** KiCad official libraries (CC-BY-SA 4.0).
[Datasheet PDF](docs/bd9611muv-e2-datasheet.pdf)