BD95861MUV-E2 from ROHM Semicon, in a VQFN-24-EP(4x4). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin	Name	Type	Function
1	VIN	power_in	Input voltage supply pin (7.5V to 18V) that sets internal duty cycle and is sensitive to supply impedance; decouple with over 10uF ceramic capacitors to PGND close to the pins.
2	VIN	power_in	Input voltage supply pin (7.5V to 18V) that sets internal duty cycle and is sensitive to supply impedance; decouple with over 10uF ceramic capacitors to PGND close to the pins.
3	VIN	power_in	Input voltage supply pin (7.5V to 18V) that sets internal duty cycle and is sensitive to supply impedance; decouple with over 10uF ceramic capacitors to PGND close to the pins.
4	VIN	power_in	Input voltage supply pin (7.5V to 18V) that sets internal duty cycle and is sensitive to supply impedance; decouple with over 10uF ceramic capacitors to PGND close to the pins.
24	VIN	power_in	Input voltage supply pin (7.5V to 18V) that sets internal duty cycle and is sensitive to supply impedance; decouple with over 10uF ceramic capacitors to PGND close to the pins.
5	PGND	power_in	Power ground pin connected to the source of the low side FET.
6	PGND	power_in	Power ground pin connected to the source of the low side FET.
7	PGND	power_in	Power ground pin connected to the source of the low side FET.
8	PGND	power_in	Power ground pin connected to the source of the low side FET.
9	PGND	power_in	Power ground pin connected to the source of the low side FET.
10	SW	passive	Switch node between high side FET source and low side FET drain, connected to the inductor and to BOOT via 0.1uF capacitor and 20 ohm resistor.
11	SW	passive	Switch node between high side FET source and low side FET drain, connected to the inductor and to BOOT via 0.1uF capacitor and 20 ohm resistor.
12	SW	passive	Switch node between high side FET source and low side FET drain, connected to the inductor and to BOOT via 0.1uF capacitor and 20 ohm resistor.
13	SW	passive	Switch node between high side FET source and low side FET drain, connected to the inductor and to BOOT via 0.1uF capacitor and 20 ohm resistor.
14	SW	passive	Switch node between high side FET source and low side FET drain, connected to the inductor and to BOOT via 0.1uF capacitor and 20 ohm resistor.
15	SW	passive	Switch node between high side FET source and low side FET drain, connected to the inductor and to BOOT via 0.1uF capacitor and 20 ohm resistor.
16	BOOT	power_in	High side FET gate driver supply pin with 0.1uF capacitor and 20 ohm resistor to SW; swings from VREG to (VIN + VREG) during switching.
17	EN	input	Enable input; regulator becomes active at 2.2V or more and the IC is in standby below 0.3V.
18	PGOOD	output	Open-drain power good output requiring a 100kΩ pull-up to VREG or another supply; leave open or tie to ground if unused.
19	VOUT	input	Output voltage sense pin connected directly to the output; ON TIME is determined by monitoring it.
20	FB	input	Output voltage feedback pin compared with REF internally; set output with feedback resistances totaling less than 50kΩ.
21	GND	power_in	Sense ground pin for all internal analog and digital power supplies.
22	VREG	power_out	Internal 5.0V supply output, active when EN is at least 2.2V, up to 10mA, with a 4.7uF capacitor to ground.
23	TEST	input	Test pin; connect to ground.
25	EP	power_in	Exposed thermal pad connected to the substrate; connect to ground.

Key specifications

Parameter	Value
Manufacturer	ROHM Semicon
Package	VQFN-24-EP(4x4)
Category	Power Management ICs
Pins	25

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter	Symbol	Min	Typ	Max	Unit	Conditions	Page
Input Voltage (abs max)	VIN			20	V	Not to exceed Pd	4
BOOT Voltage (abs max)	BOOT			27	V	Not to exceed Pd	4
BOOT-SW Voltage (abs max)	BOOT-SW			7	V	Not to exceed Pd	4
Output Voltage (abs max)	VOUT			7	V	Not to exceed Pd	4
SW Voltage (abs max)	SW			20	V	Not to exceed Pd	4
VREG Voltage (abs max)	VREG			7	V	Not to exceed Pd	4
EN Input Voltage (abs max)	EN			20	V	Not to exceed Pd	4
PGOOD Voltage (abs max)	PGOOD			7	V	Not to exceed Pd	4
Power Dissipation 1	Pd1			0.34	W	Ta 25°C (IC only)	4
Power Dissipation 2	Pd2			0.7	W	Ta 25°C, 70mm×70mm×1.6mm single-layer board	4
Power Dissipation 3	Pd3			2.2	W	Ta 25°C, 4-layer board, 6.28 mm2 pad top/bottom, 5505 mm2 on 2nd and 3rd layer	4
Power Dissipation 4	Pd4			3.55	W	Ta 25°C, 4-layer board, all layers 5505 mm2	4
Operating Temperature Range	Topr	-20		100	°C	Not to exceed Pd	4
Storage Temperature Range	Tstg	-55		150	°C		4
Junction Temperature	Tjmax			150	°C		4
Input Voltage (operating)	VIN	7.5	12	18	V	Ta=-20 to 100℃	4
VREG Voltage (operating)	VREG	4.5	5	5.5	V	Ta=-20 to 100℃	4
BOOT Voltage (operating)	BOOT	4.5		23.5	V	Ta=-20 to 100℃	4
SW Voltage (operating)	SW	-0.7		18	V	Ta=-20 to 100℃	4
BOOT-SW Voltage (operating)	BOOT-SW	4.5		5.5	V	Ta=-20 to 100℃	4
EN Input Voltage (operating)	EN	0		18	V	Ta=-20 to 100℃	4
Output Voltage (operating)	VOUT	0.8		5.5	V	Ta=-20 to 100℃; VOUT depends on VIN in some cases	4
PGOOD Voltage (operating)	PGOOD	0		5.5	V	Ta=-20 to 100℃	4
Minimum ON Time	Tonmin			200	nsec	Ta=-20 to 100℃	4
VIN Bias Current	IIN		1.2	2	mA		5
VIN Standby Current	IIN_STB		2	15	μA	EN=0V	5
EN Low Voltage	ENLOW			0.3	V		5
EN High Voltage	ENHIGH	2.2		18	V		5
EN Bias Current	IEN		3	10	μA	EN=3V	5
VREG Standby Voltage	VREG_STB			0.1	V	EN=0V	5
VREG Output Voltage	VREG	4.5	5	5.5	V	IREG=10mA	5
VREG Maximum Output Current	IREG	10			mA		5
High side FET ON Resistance	RONH		50	100	mΩ		5
Low side FET ON Resistance	RONL		30	60	mΩ		5
FB threshold Voltage	VFB	0.788	0.8	0.812	V		5
FB Input Current	IFB	-1		1	μA		5
Minimum OFF Time	TOFFMIN	200	450		nsec		5
VOUT Discharge Current	IVOUT	3	6.6		mA	VOUT=1V, EN=0V, VREG=5V	5
Over Current Protection Current Limit	IOCP	6.1	10.5		A	*3 Not tested on outgoing inspection	6
SCP Threshold Voltage	VSCP	0.48	0.56	0.64	V	VFB=0.8V 0V	6
OVP Threshold Voltage	VOVP	0.86	0.96	1.06	V	VFB=0.8V 2.0V	6
VREG UVLO Threshold Voltage	VREG_UVLO	3.75	4.2	4.65	V	VREG: Sweep up	6
VREG UVLO Hysteresis Voltage	dVREG_UVLO	100	160	220	mV	VREG: Sweep down	6
VFB Power Good Low Voltage	VFB_PL	0.61	0.68	0.75	V	VFB=0.8V 0V	6
VFB Power Good High Voltage	VFB_PH	0.65	0.72	0.79	V	VFB=0V 0.8V	6
ON Time	TON		470		nsec		5
Soft Start Time	TSOFT		1		msec		5
SCP delay time	TSCP		1		msec		6
OVP delay time	TOVP		1		msec		6
Thermal Resistance, 4-layer all layers 5505 mm2	θj-a		35.1		/W	4 layer board, all layers with 5505 mm2 copper	22
Thermal Resistance, 4-layer 6.28 mm2 top/bottom	θj-a		56.8		/W	4 layer board, 6.28 mm2 pad top and bottom, 5505 mm2 on 2nd and 3rd layer	22
Thermal Resistance, 1-layer	θj-a		181.2		/W	1 layer board, 6.28 mm2 copper pad	22

CAD (KiCad official)

Symbol: BD95861MUV-E2
Footprint: Package_DFN_QFN:QFN-24-1EP_4x4mm_P0.5mm_EP2.6x2.6mm
3D model: VQFN-24-EP(4x4) (KiCad packages3D, STEP)
3D model files: bd95861muv-e2-etched.step / bd95861muv-e2-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); bd95861muv-e2.step / bd95861muv-e2.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

Datasheet: ROHM Semicon datasheet (26 pp, sha256 1ba7dab1019bf939, retrieved 2026-10-31, tier: manufacturer)
Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-sonnet-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF

BD95861MUV-E2

Verified BD95861MUV-E2

Verification log 1 record

3D Model

Symbol & Footprint

Schematic Symbol

PCB Footprint

Datasheet

README