component
BD95831MUV-E2
Public Made by Adomby adom
ROHM Semicon DC-DC Converters, VQFN-16-EP(3x3). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
3D Model
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Symbol & Footprint
Schematic Symbol
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PCB Footprint
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Datasheet
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README
markdownBD95831MUV-E2
ROHM Semicon · DC-DC Converters · VQFN-16-EP(3x3)
BD95831MUV-E2 from ROHM Semicon, in a VQFN-16-EP(3x3). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | VIN | power_in | Input voltage supply pin (7.5V to 15V) that sets internal duty cycle and feeds the switching regulator output block; decouple with over 10µF ceramic capacitors to PGND close to the pins. |
| 2 | VIN | power_in | Input voltage supply pin (7.5V to 15V) that sets internal duty cycle and feeds the switching regulator output block; decouple with over 10µF ceramic capacitors to PGND close to the pins. |
| 3 | PGND | power_in | Power ground pin connected to the source of the low side FET. |
| 4 | PGND | power_in | Power ground pin connected to the source of the low side FET. |
| 5 | SW | power_out | Switch node between high side FET source and low side FET drain, connected to the inductor. |
| 6 | SW | power_out | Switch node between high side FET source and low side FET drain, connected to the inductor. |
| 7 | SW | power_out | Switch node between high side FET source and low side FET drain, connected to the inductor. |
| 8 | BOOT | passive | High side FET gate driver power supply pin; connect a 0.01µF capacitor between BOOT and SW, with BOOT swinging from VREG to VIN+VREG. |
| 9 | EN | input | Enable input; the regulator becomes active at 2.2V or more and enters standby below 0.3V. |
| 10 | PGOOD | tri_state | Open-drain power good output; use a 100kΩ pull-up to VREG or another supply, and leave open or short to ground if unused. |
| 11 | VOUT | input | Output voltage sense pin connected directly to the output; ON time is determined by monitoring it. |
| 12 | FB | input | Output voltage feedback pin compared with REF; set output voltage with feedback resistances totaling less than 50kΩ. |
| 13 | GND | power_in | Sense ground pin for all internal analog and digital power supplies. |
| 14 | VREG | power_out | Internal 5.0V supply output up to 10mA, active when EN is at least 2.2V; insert a 0.022µF capacitor to ground. |
| 15 | TEST | input | Test pin; connect to ground. |
| 16 | VIN | power_in | Input voltage supply pin (7.5V to 15V) that sets internal duty cycle and feeds the switching regulator output block; decouple with over 10µF ceramic capacitors to PGND close to the pins. |
| 17 | Thermal Pad | power_in | Exposed thermal pad; connect to ground. |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | ROHM Semicon |
| Package | VQFN-16-EP(3x3) |
| Category | Power Management ICs |
| Pins | 17 |
Electrical characteristics
Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| FB threshold Voltage | VFB | 0.788 | 0.8 | 0.812 | V | Ta=25℃, VIN=12V, EN=3V, VOUT=3.3V | 5 |
| FB Input Current | IFB | -1 | 1 | A | 5 | ||
| VIN Bias Current | IIN | 1.2 | 2 | mA | 5 | ||
| VIN Standby Current | IIN_STB | 2 | 15 | A | EN=0V | 5 | |
| EN Low Voltage | ENLOW | 0.3 | V | 5 | |||
| EN High Voltage | ENHIGH | 2.2 | 15 | V | 5 | ||
| EN Bias Current | IEN | 3 | 10 | A | EN=3V | 5 | |
| VREG Standby Voltage | VREG_STB | 0.1 | V | EN=0V | 5 | ||
| VREG Output Voltage | VREG | 4.5 | 5 | 5.5 | V | IREG=10mA | 5 |
| VREG Maximum Output Current | IREG | 10 | mA | 5 | |||
| High side FET ON Resistance | RONH | 85 | 170 | mΩ | 5 | ||
| Low side FET ON Resistance | RONL | 55 | 110 | mΩ | 5 | ||
| Minimum OFF Time | TOFFMIN | 200 | 450 | nsec | 5 | ||
| VOUT Discharge Current | IVOUT | 3 | 6.6 | mA | VOUT=1V, EN=0V, VREG=5V | 5 | |
| Over Current Protection Current Limit | IOCP | 3.5 | 4.5 | 6 | A | *3 Not tested on outgoing inspection | 6 |
| SCP Threshold Voltage | VSCP | 0.48 | 0.56 | 0.64 | V | VFB=0.8V → 0V | 6 |
| OVP Threshold Voltage | VOVP | 0.86 | 0.96 | 1.06 | V | VFB=0.8V → 2.0V | 6 |
| VREG UVLO Threshold Voltage | VREG_UVLO | 3.75 | 4.2 | 4.65 | V | VREG: Sweep up | 6 |
| VREG UVLO Hysteresis Voltage | dVREG_UVLO | 100 | 160 | 220 | mV | VREG: Sweep down | 6 |
| VFB Power Good Low Voltage | VFB_PL | 0.61 | 0.68 | 0.75 | V | VFB=0.8V → 0V | 6 |
| VFB Power Good High Voltage | VFB_PH | 0.65 | 0.72 | 0.79 | V | VFB=0V → 0.8V | 6 |
| ON Time | TON | 470 | nsec | 5 | |||
| Soft Start Time | TSOFT | 1 | msec | 5 | |||
| SCP delay time | TSCP | 1 | msec | 6 | |||
| OVP delay time | TOVP | 1 | msec | 6 | |||
| Input Voltage (operating) | VIN | 7.5 | 12 | 15 | V | Ta=-20 to 100℃ | 4 |
| VREG Voltage (operating) | VREG | 4.5 | 5 | 5.5 | V | Ta=-20 to 100℃ | 4 |
| BOOT Voltage (operating) | BOOT | 4.5 | 21 | V | Ta=-20 to 100℃ | 4 | |
| SW Voltage (operating) | SW | -0.7 | 15 | V | Ta=-20 to 100℃ | 4 | |
| BOOT-SW Voltage (operating) | BOOT-SW | 4.5 | 5.5 | V | Ta=-20 to 100℃ | 4 | |
| EN Input Voltage (operating) | EN | 0 | 15 | V | Ta=-20 to 100℃ | 4 | |
| Output Voltage (operating) | VOUT | 0.8 | 5.5 | V | Ta=-20 to 100℃; VOUT depends on VIN in some cases | 4 | |
| PGOOD Voltage (operating) | PGOOD | 0 | 5.5 | V | Ta=-20 to 100℃ | 4 | |
| Minimum ON Time | Tonmin | 200 | nsec | Ta=-20 to 100℃ | 4 | ||
| Input Voltage (abs max) | VIN | 15.2 | V | Ta=25℃; not to exceed Pd | 4 | ||
| BOOT Voltage (abs max) | BOOT | 21.5 | V | Ta=25℃; not to exceed Pd | 4 | ||
| BOOT-SW Voltage (abs max) | BOOT-SW | 7 | V | Ta=25℃; not to exceed Pd | 4 | ||
| VOUT Input Voltage (abs max) | VOUT | 7 | V | Ta=25℃; not to exceed Pd | 4 | ||
| SW Voltage (abs max) | SW | 15.2 | V | Ta=25℃; not to exceed Pd | 4 | ||
| VREG Voltage (abs max) | VREG | 7 | V | Ta=25℃; not to exceed Pd | 4 | ||
| EN Input Voltage (abs max) | EN | 15.2 | V | Ta=25℃; not to exceed Pd | 4 | ||
| PGOOD Voltage (abs max) | PGOOD | 7 | V | Ta=25℃; not to exceed Pd | 4 | ||
| Power Dissipation 1 | Pd1 | 0.27 | W | Ta≧25°C (IC only), 2.2mW/°C | 4 | ||
| Power Dissipation 2 | Pd2 | 0.62 | W | Ta≧25°C, 70mm×70mm×1.6mm single-layer board, 6.28mm2 copper pad, 5.0mW/°C | 4 | ||
| Power Dissipation 3 | Pd3 | 1.77 | W | Ta≧25°C, 4-layer board, 6.28mm2 pad top/bottom, 5505mm2 pad on 2nd and 3rd layer, 14.1mW/°C | 4 | ||
| Power Dissipation 4 | Pd4 | 2.66 | W | Ta≧25°C, 4-layer board, all layers 5505mm2 pads, 21.3mW/°C | 4 | ||
| Operating Temperature Range | Topr | -20 | 100 | ℃ | Not to exceed Pd | 4 | |
| Storage Temperature Range | Tstg | -55 | 150 | ℃ | 4 | ||
| Junction Temperature | Tjmax | 150 | ℃ | 4 | |||
| Thermal resistance, 4-layer board all layers 5505mm2 | θj-a | 47 | ℃/W | 4 layer board, all layers 5505 mm2 copper pads | 22 | ||
| Thermal resistance, 4-layer board 6.28mm2 top/bottom | θj-a | 70.62 | ℃/W | 4 layer board, 6.28 mm2 pad top and bottom, 5505 mm2 pad on 2nd and 3rd layer | 22 | ||
| Thermal resistance, 1-layer board | θj-a | 201.6 | ℃/W | 1 layer board, 6.28 mm2 copper pad | 22 |
CAD (KiCad official)
- Symbol:
BD95831MUV-E2 - Footprint:
Package_DFN_QFN:QFN-16-1EP_3x3mm_P0.5mm_EP1.7x1.7mm - 3D model: VQFN-16-EP(3x3) (KiCad packages3D, STEP)
- 3D model files:
bd95831muv-e2-etched.step/bd95831muv-e2-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);bd95831muv-e2.step/bd95831muv-e2.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: ROHM Semicon datasheet (26 pp, sha256
80d7f43bad362131, retrieved 2026-10-27, tier: manufacturer) - Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-sonnet-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).