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BD93291EFJ-E2

ROHM Semicon · DC-DC Converters · SOIC-8

BD93291EFJ-E2 from ROHM Semicon, in a SOIC-8. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 SW output Connects the inductor switching node of the high-voltage buck converter, tied to the high-side FET source and low-side FET drain, with an SW voltage range of -0.5V to 26V and an absolute maximum of 30V.
2 BST power_out Connect a 0.1uF bootstrap capacitor between BST and SW to generate the high-side N-channel MOSFET gate drive voltage, with BST rated at VSW+7V.
3 EN input Enable input where high (2.3V typ.) activates the output and low (1.8V typ.) shuts the IC down, with an absolute maximum of 30V.
4 VIN power_in Supply input for the high-voltage buck converter with an operating range of 8.0V to 26V (absolute maximum 30V), and a 10uF ceramic bias capacitor is recommended.
5 GND power_in Power ground for the low-side MOSFETs of both buck converters and analog ground, which must be the minimum potential in the system under all operating conditions.
6 FBL input Output voltage feedback input of the low-voltage buck converter, regulated to a feedback voltage of 0.8V ±1.5%.
7 SWL output Connects the inductor switching node of the low-voltage buck converter, with a SWL voltage range of -0.5V to 5.5V and an absolute maximum of 7.0V.
8 VOUT power_in Supply pin for the low-voltage buck converter (5.0V) and output voltage feedback for the high-voltage buck converter, with an absolute maximum of 7.0V, and a 10uF ceramic bias capacitor is recommended.

Key specifications

Parameter Value
Manufacturer ROHM Semicon
Package SOIC-8
Category Power Supply Chip
Pins 8

Materials and finish

As the datasheet states them (page.json metadata.appearance; the 3D model's colours follow it).

Part Material Colour / plating Datasheet says Page
contacts copper Especially, C_CO3 between VOUT and GND must be placed near the VOUT pin, and keep the distance "b" less than 2mm. ・When there is unused area on PCB, please arrange the copper foil plain of DC nodes, s 15

CAD (KiCad official)

  • Symbol: BD93291EFJ-E2
  • Footprint: Package_SO:SOIC-8_3.9x4.9mm_P1.27mm
  • 3D model: SOIC-8 (KiCad packages3D, STEP)
  • 3D model files: bd93291efj-e2-etched.step / bd93291efj-e2-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); bd93291efj-e2.step / bd93291efj-e2.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: ROHM Semicon datasheet (24 pp, sha256 1dcc194d965ac6b0, retrieved 2026-10-26, tier: manufacturer)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF