# BD7F100HFN-LBTR

**ROHM Semicon** · DC-DC Converters · SOP-8-EP

BD7F100HFN-LBTR from ROHM Semicon, in a SOP-8-EP. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

## Pinout

| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | AGND | power_in | Analog system GND for the control circuitry, separate from the power-system ground PGND. |
| 2 | SDX/EN | input | Shutdown/enable control: the internal regulator is shut down when this terminal is below 0.9V (Typ), and soft start enables above 2.0V (Typ). |
| 3 | COMP | passive | Load current compensation pin used to set up the output voltage compensation; the datasheet gives no numeric limit for this pin. |
| 4 | REF | input | Output voltage setup pin whose voltage is the feedback voltage compared against the internal VREF in the comparator. |
| 5 | FB | input | Output voltage setup pin; the output voltage is set by two external resistors and the transformer turns ratio. |
| 6 | PGND | power_in | Power-system GND for the switching power stage. |
| 7 | SW | output | Switching output driven by the built-in N-channel MOSFET; the SW terminal operating voltage is 50V (Max) and it goes Hi-Z during VIN undervoltage lockout. |
| 8 | VIN | power_in | Power supply input with a 3V to 40V operating range; VIN UVLO trips below 2.5V (Typ) and recovers at 2.65V (Typ). |
| 9 | EP | passive | Exposed pad (from the footprint; not named in the datasheet pin table). |

## Key specifications

| Parameter | Value |
|---|---|
| Manufacturer | ROHM Semicon |
| Package | SOP-8-EP |
| Category | Power Supply Chip |
| Pins | 9 |

## Electrical characteristics

Limits as printed in the datasheet (page.json `metadata.characteristics` carries them as data).

| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| VIN Input Power Voltage | VIN |  |  | 45 | V | Not to exceed Power Dissipation (Pd) (Note 1) | 4 |
| SW Terminal Voltage | VSW |  |  | 60 | V |  | 4 |
| REF Terminal Voltage | VREF |  |  | 7 | V |  | 4 |
| COMP Terminal Voltage | VCOMP |  |  | 7 | V |  | 4 |
| Power Dissipation | Pd |  |  | 1.75 | W | One-layer glass-epoxy board 70mm x 70mm x 1.6mm, 65% copper foil; reduced by 14.0mW/°C above 25°C (Note 2) | 4 |
| Storage Temperature Range | Tstg | -55 |  | 150 | °C |  | 4 |
| Maximum Junction Temperature | Tjmax |  |  | 150 | °C |  | 4 |
| VIN Input Power Voltage (recommended) | VIN | 3 | 24 | 40 | V |  | 4 |
| SW Terminal Voltage (recommended) | VSW |  |  | 50 | V |  | 4 |
| Junction Temperature | Tj | -40 |  | 125 | °C | Life time is derated at junction temperature greater than 125°C (Note 4) | 4 |
| Quiescent Current | IST |  | 0 | 10 | µA | VSDX/EN = 0V | 5 |
| Operating Current | ICC |  | 2 | 4 | mA | VSDX/EN = 2.5V; VREF = 2V (at PFM operation) | 5 |
| UVLO Detection Voltage | VUVLO | 2.3 | 2.5 | 2.7 | V | VIN falling | 5 |
| UVLO Hysteresis Voltage | VUVLO_HYS | 0.1 | 0.15 | 0.2 | V |  | 5 |
| Shutdown Voltage | VSDX | 0.3 | 0.9 | 1.5 | V |  | 5 |
| Enable Voltage | VEN | 1.9 | 2 | 2.1 | V | VSDX/EN rising | 5 |
| Enable Hysteresis Voltage | VEN_HYS | 0.15 | 0.2 | 0.25 | V |  | 5 |
| SDX/EN Input Current | ISDX/EN |  | 0 | 1 | µA | VSDX/EN=2V | 5 |
| Reference Voltage | VREF | 0.768 | 0.78 | 0.792 | V |  | 5 |
| Over Current Limit | ILIMIT | 1 | 1.25 | 1.5 | A |  | 5 |
| ON-Resistance | RON |  | 0.5 |  | Ω | Between SW - PGND terminals | 5 |
| Switching Frequency | fSW |  | 400 |  | kHz | At PWM operation (Duty=40%) | 5 |
| Minimum ON Time | tON_MIN |  | 350 |  | ns |  | 5 |
| Minimum OFF Time | tOFF_MIN |  | 300 |  | ns |  | 5 |
| Maximum OFF Time | tOFF_MAX |  | 20 |  | µs |  | 5 |
| Soft Start Time | tSS |  | 6 |  | ms | 0V to (VREF×90%) | 5 |

## CAD (KiCad official)

- Symbol: `BD7F100HFN-LBTR`
- Footprint: `Package_SO:SOIC-8-1EP_3.9x4.9mm_P1.27mm_EP2.29x3mm`
- 3D model: SOP-8-EP (KiCad packages3D, STEP)
- 3D model files: `bd7f100hfn-lbtr-etched.step` / `bd7f100hfn-lbtr-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `bd7f100hfn-lbtr.step` / `bd7f100hfn-lbtr.glb` are the bare package body.

## Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

- **Datasheet:** [ROHM Semicon datasheet](https://jlcpcb.com/api/file/downloadByFileSystemAccessId/8589831499890790400) (31 pp, sha256 `b6320dae678ea33a`, retrieved 2026-10-18, tier: lcsc)
- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.3`, primary `claude-haiku-5-5` (text), consensus `claude-sonnet-5-5` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
- **CAD:** KiCad official libraries (CC-BY-SA 4.0).

[Datasheet PDF](docs/bd7f100hfn-lbtr-datasheet.pdf)