Base Scaffold Control Panel

@@ -0,0 +1,106 @@+# Control Panel: Scaffold — Datasheet++**Control Panel: Scaffold V2.1.0** · Datasheet · 2026-09-07++---++## Features++- User-power and I/O dock for the Control Panel: Workcell, 160 × 45 mm, 4-layer+- Three isolated supply rails passed to a 63-contact machine field: PS1 0–60 V/12 A, PS2 5 V/10 A switched, PS3 spare+- Hosted RP2350A Mini molecule with 26 USER_IO lines on the field, SWD and UART to the Workcell's PiProbe+- Role-aware USB-C 2.0 with PS2-derived VBUS behind a latching eFuse and an anti-series P-FET block+- AT24CS32 ID EEPROM with a factory 128-bit serial number on the dock's i2c-0 bus+- Per-rail ground bond jumpers JP1–JP3 (large machine pins), USB CC override JP4++## Description++The Scaffold is the user-facing half of the Control Panel pair. It docks to the Workcell through a Samtec ET60T blade connector, receives the three user rails plus 5 V and 3.3 V logic supplies, and presents everything on a field of machine contacts for the user's fixtures. An RP2350A molecule gives 26 GPIO on the field and is programmed, reset and booted from the Workcell over the dock, so the user never needs a cable. Every function was exercised on the bench in the Rev 1.1 test campaign, §9 of the Control Panel Test Procedure.++## Absolute maximum ratings++| Parameter | Min | Max | Unit | Basis |+|---|---|---|---|---|+| +PS1 blade | 0 | 60 | V | design rating, passed through |+| +PS2 blade | 0 | 5.5 | V | TPS259530 input; OV clamp 5.7 V (SLVSE57C) |+| +PS3 blade | 0 | 24 | V | design rating |+| PS1 / PS2 / PS3 field current | | 12 / 10 / 10 | A | 4 + 3 contacts per rail |+| USB-C VBUS load | | 3.33 | A | eFuse U1 trip, bench |+| USER_IO voltage | −0.3 | 3.6 | V | RP2350A GPIO |+| USER_IO current, per pin | | 12 | mA | RP2350A drive setting |+| −PSx to GND | −2.5 | +2.5 | V | with JP1–JP3 open |++## Recommended operating conditions++| Parameter | Min | Typ | Max | Unit |+|---|---|---|---|---|+| +PS4_SENS logic supply from the dock | 4.75 | 5.0 | 5.25 | V |+| +3v3 from the dock | 3.2 | 3.3 | 3.4 | V |+| USB-C VBUS out (host role) | 4.75 | 5.0 | 5.25 | V |+| USB-C VBUS load, continuous | | | 3.0 | A |+| SWD clock | | 1 | 31 | MHz |+| Debug UART | | 115 200 | 3 000 000 | baud |++## Electrical characteristics — bench, Rev 1.1++| Parameter | Condition | Value | Limit | Ref |+|---|---|---|---|---|+| USER_IO toggle | cpw-iostress, all 26 lines | 250 kHz, 0 ↔ 3.35 V | 26 / 26 | 9.1.2 |+| USB-C VBUS route resistance | 0.5–3.0 A | 130 mΩ | | 9.1.3 |+| USB-C eFuse trip | ramp 0.1 A steps | 3.33 A | rated 3.3 A, ≤ 4.0 A | 9.1.3 |+| Client-role enumeration | PC host | RP2350 FAT volume, 127.86 MB | | 9.2.1 |+| Client-role back-feed | PC attached, PS2 off | 0 V at the +PS2 contacts | 0 V | 9.2.2 |+| Host-role VBUS | PS2 on | 5.0 V sourced, device mounted | | 9.2.3, 9.2.4 |+| Client-role transfer | 16 MiB write | 1.06 MB/s | 0.5–1.1 | 9.2.5 |+| SWD scan | through the dock | both Cortex-M33 cores | clean | 9.3.1 |+| SWD maximum clock | | 31 000 kHz clean | | 9.3.2 |+| UART echo | 115 200 / 1 M / 3 M | intact | | 9.3.6 |+| Boot / reset control | 20 cycles from the CM5 | 20 / 20 | 20 / 20 | 9.3.8 |+| Flash erase | 2 MiB, 512 sectors | 7.5 s at 1 MHz | | 9.1.4 |+| ID EEPROM | i2c-0 | ACK at 0x50 and 0x58 | | 3.1 |++Ref = step in the Control Panel Test Procedure Rev 1.1.++## Machine contact field (V2.1.0)++| Contacts | Net | Notes |+|---|---|---|+| MC1–MC4 | +PS1_SENS | PS1 rail |+| MC5–MC8 | +PS2_RLY | PS2 rail, switched |+| MC9–MC12 | +PS3_SENS | PS3 rail |+| MC13, MC14 | SPARE1, SPARE2 | CM5 GPIO14 / GPIO15 through the dock |+| MC15, MC16, MC55–MC63 | GND | |+| MC17 | USB2_VBUS | USB-C VBUS at the field (JP4 enables it without a CC-wired device) |+| MC18, MC19 | MCU_USB2_D+, D− | RP2350 USB |+| MC20–MC22 | −PS1 | isolated return, bonded by JP1 |+| MC23–MC25 | −PS2 | isolated return, bonded by JP2 |+| MC26–MC28 | −PS3 | isolated return, bonded by JP3 |+| MC29–MC36 | USER_IO 29, 28, 27, 26, 25, 24, 23, 22 | |+| MC37–MC44 | USER_IO 19, 18, 17, 16, 15, 14, 13, 12 | |+| MC45–MC54 | USER_IO 9, 8, 7, 6, 5, 4, 3, 2, 1, 0 | |++RP2350A GPIO10, 11, 20 and 21 are reserved by the molecule (LEDs and debug UART).++## Dock — J2 (Samtec ET60T-S03)++Pins 1–2 SPARE1/2 · 3 SWD · 8 SWCLK · 4 MCU_BOOT · 5 MCU_RST · 6/7 PROM_I2C-0 SDA/SCL · 9/10 DEBUG TX/RX · 16/17 +PS4_SENS · 19/20 +3v3 · 11–15, 18, 21–25 GND · blades P1/P2/P3 with five + and five − contacts each. MCU_BOOT and MCU_RST are active-low and parked low by the Workcell at boot.++## Key components++| Ref | Part | Function | Document |+|---|---|---|---|+| U1 | TPS259530DSGR | VBUS eFuse, latch-off, 5.7 V OV clamp | TI SLVSE57C |+| U2 | RP2350A Mini molecule | User MCU, 26 USER_IO | Raspberry Pi RP2350 datasheet |+| U3 | TUSB321RWBR | USB-C CC controller, role detect | TI SLLSEO6C |+| U4 | AT24CS32-STUM | 32 kbit ID EEPROM, 128-bit serial, 1.7–5.5 V | Microchip DS20006341B |+| U5 | TPD2EUSB30DRTR | USB D± ESD | TI SLVSAC2G |+| Q1 | AO4805 | Anti-series P-FET VBUS block | Alpha & Omega AO4805 |+| J1 | GT-USB-7090C | USB-C 2.0 receptacle | |+| J2 | Samtec ET60T-S03 | Dock | |++## Revision++| Board | Change | Date |+|---|---|---|+| V2.1.0 | AT24CS32 ID EEPROM on i2c-0; TPS259530 latching eFuse; anti-series VBUS block; spares reduced to GPIO14/15 | 2026-08 |+| V2.0.1 | Name and version silkscreen, LED silkscreen | 2026-07 |