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AXP2101

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X Powers Tech Power Management - Specialized, QFN-40-EP(5x5). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

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AXP2101

X Powers Tech · Power Management - Specialized · QFN-40-EP(5x5)

AXP2101 from X Powers Tech, in a QFN-40-EP(5x5). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 CHGLED output Charge status output indicating various charger operating states.
2 VREF power_in Internal reference voltage pin; 1uF/6.3V capacitor shown in the typical application.
3 GND power_in Analog ground for interrupt analog and digital circuits.
4 FB3 passive DCDC3 feedback pin.
5 LX3 passive Inductor pin for DCDC3.
6 VIN3 power_in DCDC3 input source.
7 VIN4 power_in DCDC4 input source.
8 LX4 passive Inductor pin for DCDC4.
9 FB4 passive DCDC4 feedback pin and switch input source.
10 CPUSLDO power_out Output pin of CPUSLDO (0.5~1.4V, up to 30mA per features list).
11 DLDO2/DC4SW power_out Output pin of DLDO2, configurable as the output pin of DC4SW.
12 BLDO1 power_out Output pin of BLDO1.
13 BLDOIN power_in BLDO input source.
14 BLDO2 power_out Output pin of BLDO2.
15 ALDO4 power_out Output pin of ALDO4.
16 ALDO3 power_out Output pin of ALDO3.
17 ALDOIN power_in ALDO input source.
18 ALDO1 power_out Output pin of ALDO1.
19 ALDO2 power_out Output pin of ALDO2.
20 DLDO1/DC1SW power_out Output pin of DLDO1, configurable as the output pin of DC1SW.
21 FB1 passive DCDC1 feedback pin.
22 LX1 passive Inductor pin for DCDC1.
23 VIN1 power_in DCDC1 input source.
24 VIN2 power_in DCDC2 input source.
25 LX2 passive Inductor pin for DCDC2.
26 FB2 input DCDC2 feedback pin.
27 VBACKUP power_in Input pin of the backup battery.
28 VRTC power_out RTC power output.
29 PWROK bidirectional Power good indication output.
30 PWRON bidirectional Power on-off key input with internal 100k pull-up to VINT.
31 TS input Battery temperature qualification input for an NTC thermistor to GND; a current source is injected and charging suspends when TS is out of range; can also be an external input signal.
32 GPIO1 bidirectional GPIO1 output pin, configurable to RTCLDO or FB5 of DCDC5.
33 BAT passive Battery connection point with the internal BATFET between BAT and SYS; connect a 1uF capacitor close to the pin.
34 VSYS passive System connection point with the internal BATFET between BAT and SYS; keeps SYS above minimum system voltage; connect two 22uF capacitors close to the pin.
35 SW passive Inductor pin for the buck converter.
36 VMID power_out VMID power output.
37 VBUS power_in VBUS input.
38 IRQ output Open-drain interrupt output reporting charger status and faults; connect to a logic rail via a 4.7kΩ resistor.
39 SCK input Serial interface pin (SCK) needing a 2.2kΩ pull-up; table text calls it the data pin.
40 SDA bidirectional Serial interface pin (SDA) needing a 2.2kΩ pull-up; table text calls it the clock pin.
41 EP passive Exposed pad (from the footprint; not named in the datasheet pin table).

Key specifications

Parameter Value
Manufacturer X Powers Tech
Package QFN-40-EP(5x5)
Category Power Management (PMIC)
Pins 41

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
VBUS voltage range (with respect to GND) VBUS -0.3 12 V with respect to GND 6
Other pins voltage (excluding VBUS, PGND, GND) -0.3 7 V 6
PGND to GND voltage -0.3 0.3 V 6
Operating free-air temperature range Ta -40 85 ℃ 6
Junction temperature range TJ -40 125 ℃ 6
Storage temperature range Ts -65 150 ℃ 6
Maximum soldering temperature (at leads) TLEAD 30 ℃ at leads, 10 sec 6
Input voltage (VBUS) VIN 3.9 5.5 V 6
Input current (VBUS) IIN 2 A 6
Output current ISYS 2 A 6
Battery voltage VBAT 4.4 V 6
Charging current IBAT 1 A 6
Junction-to-ambient thermal resistance θJA 30 ℃/W JEDEC JESD51 calculation 6
Junction-to-board thermal resistance θJB 10.8 ℃/W JEDEC JESD51 calculation 6
Junction-to-case (top) thermal resistance θJC 22.8 ℃/W JEDEC JESD51 calculation 6
Target charge voltage accuracy -0.5 0.5 % testing ambient temperature 25℃, target voltage 4.2V 14
Target charge voltage setting range (VREG) VREG 4 4.6 V settable via reg64[2:0]; steps 4.0/4.1/4.2/4.35/4.4/4.6 V 14
Fast charge current setting range (ICHG) ICHG 0 1000 mA settable via reg62[4:0] 14
Pre-charge current setting range (IPRE-CHG) IPRE-CHG 0 200 mA settable via reg61[3:0] 14

CAD (KiCad official)

  • Symbol: AXP2101
  • Footprint: Package_DFN_QFN:QFN-40-1EP_5x5mm_P0.4mm_EP3.6x3.6mm
  • 3D model: QFN-40-EP(5x5) (KiCad packages3D, STEP)
  • 3D model files: axp2101-etched.step / axp2101-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); axp2101.step / axp2101.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: X Powers Tech datasheet (52 pp, sha256 0745cc5e6c21d935, retrieved 2026-10-19, tier: lcsc)
  • Datasheet language: Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF