Loads when you scroll to it. Unloads after 5 minutes in the background.

Symbol & Footprint

Schematic Symbol

Open full view ↗
Loads when you scroll to it. Unloads after 5 minutes in the background.

PCB Footprint

Open full view ↗
Loads when you scroll to it. Unloads after 5 minutes in the background.
Loads when you scroll to it. Unloads after 5 minutes in the background.
Download PDF
Contents

README

markdown

AW87318FCR

AWINIC(Shanghai Awinic Tech) · Audio Power OpAmps · BGA-16

AW87318FCR from AWINIC(Shanghai Awinic Tech), in a BGA-16. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
A1 INP input Positive audio input; absolute maximum voltage is -0.3V to VDD+0.3V.
A2 INN input Negative audio input; absolute maximum voltage is -0.3V to VDD+0.3V.
A3 VDD power_in Power supply; absolute maximum VDD voltage is -0.3V to 6V.
A4 SHDN input Chip power down pin, active low, driven by one-wire pulse control.
B1 C2N passive Negative terminal of the charge pump flying capacitor CF2; absolute maximum voltage is -0.3V to VDD+0.3V.
B2 C2N passive Negative terminal of the charge pump flying capacitor CF2; absolute maximum voltage is -0.3V to VDD+0.3V.
B3 VDD power_in Power supply; absolute maximum VDD voltage is -0.3V to 6V.
B4 VOP output Positive audio output; absolute maximum voltage is -0.3V to PVDD+0.3V.
C1 C1N passive Negative terminal of the charge pump flying capacitor CF1; absolute maximum voltage is -0.3V to VDD+0.3V.
C2 GND power_in Ground.
C3 GND power_in Ground.
C4 GND power_in Ground.
D1 C2P passive Positive terminal of the charge pump flying capacitor CF2; absolute maximum voltage is -0.3V to PVDD+0.3V.
D2 C1P passive Positive terminal of the charge pump flying capacitor CF1; absolute maximum voltage is -0.3V to PVDD+0.3V.
D3 PVDD power_out Charge pump output; absolute maximum PVDD voltage is -0.3V to 7V.
D4 VON output Negative audio output; absolute maximum voltage is -0.3V to PVDD+0.3V.

Key specifications

Parameter Value
Manufacturer AWINIC(Shanghai Awinic Tech)
Package BGA-16
Category Operational Amplifier/Comparator
Pins 16

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
Power supply voltage VDD (absolute maximum) VDD -0.3 6 V 7
Charge pump output PVDD voltage (absolute maximum) PVDD -0.3 7 V 7
VOP, VON, C1P, C2P voltage (absolute maximum) -0.3 V max PVDD+0.3V 7
C1N, C2N voltage (absolute maximum) -0.3 V max VDD+0.3V 7
Input pin INP, INN voltage (absolute maximum) -0.3 V max VDD+0.3V 7
Operating free-air temperature TA -40 85 °C 7
Maximum junction temperature TJMAX 165 °C 7
Storage temperature TSTG -40 150 °C 7
Lead temperature (soldering) 260 °C 10 seconds 7
ESD Human Body Model -6 6 kV HBM 7
ESD Charged Device Model -2 2 kV CDM 7
Latch-up positive trigger current +IT 450 mA JEDEC STANDARD NO.78D 7
Latch-up negative trigger current -IT -450 mA JEDEC STANDARD NO.78D 7
Power supply voltage VDD 3 5.5 V 9
SHDN high input voltage VIH 1.3 V max VDD 9
SHDN low input voltage VIL 0 0.45 V 9
Output offset voltage /VOS/ -30 0 30 mV VIN=0V, VDD=3.0V to 5.5V 9
Charge pump frequency FCP 0.79 1.06 1.33 MHz VDD=3.0V to 5.5V 9
Soft-start time TST 1 1.2 1.4 ms No load, COUT=4.7μF 9
Current limit when PVDD short to ground IL 200 300 400 mA PVDD short to ground 9
Quiescent current Iq 10 15 mA VDD=4.2V, Vin=0, no load 9
Modulation frequency Fosc 600 800 1000 kHz VDD=3.0V to 5.5V 9
Mode1 Multi-Level AGC power Pagc 1.08 1.2 1.32 W VDD=4.2V, RL=8Ω+33μH 9
Mode1 Multi-Level AGC power Pagc 1.44 1.6 1.76 W VDD=4.2V, RL=6Ω+33μH 9
Mode1 Multi-Level AGC power Pagc 2.16 2.4 2.64 W VDD=4.2V, RL=4Ω+15μH 9
Mode2 Multi-Level AGC power Pagc 0.99 1.1 1.21 W VDD=4.2V, RL=8Ω+33μH 9
Mode2 Multi-Level AGC power Pagc 1.35 1.5 1.65 W VDD=4.2V, RL=6Ω+33μH 9
Mode2 Multi-Level AGC power Pagc 1.98 2.2 2.42 W VDD=4.2V, RL=4Ω+15μH 10
Mode3 Multi-Level AGC power Pagc 0.9 1 1.1 W VDD=4.2V, RL=8Ω+33μH 10
Mode3 Multi-Level AGC power Pagc 1.17 1.3 1.43 W VDD=4.2V, RL=6Ω+33μH 10
Mode3 Multi-Level AGC power Pagc 1.8 2 2.2 W VDD=4.2V, RL=4Ω+15μH 10
Mode3 Multi-Level AGC power Pagc 2.16 2.4 2.64 W VDD=4.2V, RL=3Ω+15μH 10
Shutdown current ISD 2 μA VDD=3.6V, SHDN=0V 9
Thermal AGC start temperature threshold TTG 150 °C 9
Thermal AGC exit temperature threshold TTGR 130 °C 9
Over temperature protection threshold TSD 160 °C 9
Over temperature protection recovery threshold TSDR 120 °C 9
Start-up time TON 40 ms 9
PVDD output voltage PVDD 6.05 V VDD>4V 9
OVP hysteresis voltage Vhys 50 mV VDD>4V 9
Charge pump efficiency ηCP 93 % VDD=3.6V, Iload=200mA 9
Efficiency η 83 % VDD=3.6V, Po=1.0W, RL=8Ω+33μH 9
Gain Av 16.6 V/V External input resistance=3kΩ 9
Recommended max input voltage Vin 1 Vp VDD=3.0V to 5.5V 9
Internal input resistor Rini 6.6 kΩ Mode1 to Mode7, and Mode10 9
Input high pass filter corner frequency Fhin 166 Hz Cin=100nF, external input resistor=3kΩ 9
Thermal resistance junction-to-ambient, AW87318FCR θJA 76.5 °C/W 7
Power supply rejection ratio PSRR -68 dB VDD=4.2V, Vp-p_sin=200mV, 217Hz 10
Signal-to-noise ratio SNR 98.8 dB VDD=4.2V, Po=1.7W, THD+N=1%, RL=8Ω+33μH, Av=8V/V 10
Signal-to-noise ratio SNR 98.2 dB VDD=4.2V, Po=2.0W, THD+N=1%, RL=6Ω+33μH, Av=8V/V 10
Output noise voltage Vn 43 μVrms VDD=4.2V, f=20Hz to 20kHz, input ac grounded, Av=8V/V, A-weighting 10
Output noise voltage Vn 48 μVrms VDD=4.2V, f=20Hz to 20kHz, input ac grounded, Av=12V/V 10
Output noise voltage Vn 57 μVrms VDD=4.2V, f=20Hz to 20kHz, input ac grounded, Av=16V/V 10
Total harmonic distortion+noise THD+N 0.008 % VDD=3.6V, Po=1W, RL=8Ω+33μH, f=1kHz, Mode1 10
Total harmonic distortion+noise THD+N 0.009 % VDD=3.6V, Po=1W, RL=6Ω+33μH, f=1kHz, Mode10 10

Materials and finish

As the datasheet states them (page.json metadata.appearance; the 3D model's colours follow it).

Part Material Colour / plating Datasheet says Page
contacts copper 4. Ferrite beads and filter capacitors should be close to VON and VOP pins. The trace from output pins to speaker should be short and wide. The copper width is recommended to be larger than 0.5mm (20m 26

CAD (KiCad official)

  • Symbol: AW87318FCR
  • Footprint: Package_BGA:BGA-16_1.92x1.92mm_Layout4x4_P0.5mm
  • 3D model: BGA-16 (KiCad packages3D, STEP)
  • 3D model files: aw87318fcr-etched.step / aw87318fcr-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); aw87318fcr.step / aw87318fcr.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: AWINIC(Shanghai Awinic Tech) datasheet (33 pp, sha256 0aa5deb0f7e63a75, retrieved 2026-10-27, tier: lcsc)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF