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AW8646QNR

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AWINIC Shanghai Awinic Tech Stepper Motor Driver, QFN-24-EP(4x4). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

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Contents

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AW8646QNR

AWINIC Shanghai Awinic Tech · Stepper Motor Driver · QFN-24-EP(4x4)

AW8646QNR from AWINIC Shanghai Awinic Tech, in a QFN-24-EP(4x4). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 AO1 output H-bridge A output; continuous phase node voltage limited to -0.3V to (VDD+0.6)V.
2 ASEN passive Sense output of bridge A; if current regulation is not required it must connect to GND, and continuous input is limited to -0.6V to 0.6V.
3 AO2 output H-bridge A output; continuous phase node voltage limited to -0.3V to (VDD+0.6)V.
4 BO2 output H-bridge B output; continuous phase node voltage limited to -0.3V to (VDD+0.6)V.
5 BSEN passive Sense output of bridge B; if current regulation is not required it must connect to GND, and continuous input is limited to -0.6V to 0.6V.
6 BO1 output H-bridge B output; continuous phase node voltage limited to -0.3V to (VDD+0.6)V.
7 nFAULT output Pulled low when a failure occurs; open-drain output that requires an external pull-up (R1 >5kΩ to VCC per Table 1).
8 MODE0 input Tri-level input, low bit of the step mode setting (full step up to 1/32 step) per Table 2.
9 MODE1 input Tri-level input, high bit of the step mode setting (full step up to 1/32 step) per Table 2.
10 TOFF input Tri-level input setting the PWM current-control off-time: Hi-Z 10 µs, GND 20 µs, VREG 30 µs per Table 3.
11 nEN input Driver enable input; logic low enables the device outputs and logic high disables them.
12 STEP input Step input; a rising or falling edge (depending on step mode) advances the sequencer by one step.
13 DIR input Direction input that sets the direction of stepping.
14 VREF power_in Full-scale current reference input whose voltage sets the full-scale current; short to VREG to use the internal 3.3V reference, with absolute maximum range -0.3V to 3.6V.
15 VDD power_in Motor power supply input, operating range 3V to 12V (absolute maximum 16V).
16 NC unconnected No connect; unused pin.
17 VREG power_out Internal regulator output providing the logic supply, 3.13V to 3.47V (3.3V typical) for VDD >4V and 0 to 1 mA load; requires a 2.2µF, 10V ceramic capacitor to GND.
18 GND power_in Ground; both this pin and the device thermal pad must be connected to ground.
19 ADECAY input Adaptive Decay mode control: logic high enables Adaptive Decay, logic low selects decay modes via D0 and D1; state is only evaluated when exiting sleep mode.
20 T0 input Tri-level input that scales the torque current from 100% to 12.5% in 12.5% steps together with T1 per Table 4.
21 T1 input Tri-level input that scales the torque current from 100% to 12.5% in 12.5% steps together with T0 per Table 4.
22 D0 input Tri-level decay mode setting pin, combined with D1 per Table 5.
23 nSLEEP input Sleep mode input; logic high enables the device and logic low enters low-power sleep mode; internal pull-down.
24 D1 input Tri-level decay mode setting pin, combined with D0 per Table 5.
25 EPAD power_in Thermal pad that must be connected to GND.

Key specifications

Parameter Value
Manufacturer AWINIC Shanghai Awinic Tech
Package QFN-24-EP(4x4)
Category Motor Driver ICs
Pins 25

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
VDD operating voltage VDD 3 5 12 V 7
VDD operating supply current IVDD 1 2.5 4 mA VDD = 5 V, excluding winding current, nSLEEP = 1, nEN = 0 or 1 7
VDD sleep mode supply current IVDDQ 0.1 1 A VDD = 5 V, nSLEEP = 0, nEN = 0 or 1 7
VREG voltage VREG 3.13 3.3 3.47 V VDD > 4 V, IOUT = 0 A to 1 mA 7
Input logic low voltage VIL 0 0.45 V 7
Input logic high voltage VIH 1.3 5.5 V 7
Input logic low current IIL -1 1 A VIN = 0 V 7
Input logic high current IIH 1 40 A VIN = 5 V 7
Tri-level input logic low voltage VIL 0 0.45 V 7
Tri-level input logic high voltage VIH 1.3 5.5 V 7
Tri-level input logic low current IIL -22 -1 A VIN = 0 V 7
Tri-level input logic high current IIH 1 40 A VIN = 5 V 7
Output logic high leakage IOH -1 1 A VO = 3.3 V 7
Power supply voltage (VDD) VDD -0.3 16 V 6
Power supply voltage ramp rate (VDD) 0 2 V/s 6
Internal regulator voltage VREG -0.3 3.6 V 6
Analog input pin voltage VREF -0.3 3.6 V 6
Control pin voltage -0.3 7 V nEN, STEP, DIR, T0, T1, MODE0, MODE1, D0, D1, TOFF, nSLEEP, nFAULT, ADECAY 6
Continuous phase node pin voltage -0.3 V AO1, AO2, BO1, BO2; max printed as (VDD+0.6)V 6
Continuous shunt amplifier input pin voltage -0.6 0.6 V ASEN, BSEN 6
ESD HBM (Human Body Model) -4 4 kV Human Body Model 6
ESD CDM (Charge Device Model) -1.5 1.5 kV Charge Device Model 6
Latch-up +IT 200 mA JEDEC STANDARD NO.78E 6
Latch-up -IT -200 mA JEDEC STANDARD NO.78E 6
Operating free-air temperature range -40 85 °C 6
Maximum operating junction temperature TJMAX 165 °C 6
Storage temperature TSTG -65 150 °C 6
Lead temperature 260 °C soldering 10 seconds 6
Sleep time tSLEEP 0.7 ms nSLEEP = 0 to sleep mode 7
Wake time tWAKE 0.5 ms nSLEEP = 1 to output transition 7
Power-on time tON 0.5 ms VDD > VUVLO rising to output transition 7
Pulldown resistance (nEN, STEP, DIR, ADECAY) RPD 200 kΩ nEN, STEP, DIR, ADECAY 7
Pulldown resistance (nSLEEP) RPD 500 kΩ nSLEEP 7
Input deglitch time tDEG 200 ns 7
Propagation delay tPROP 600 ns STEP edge to current change 7
Input logic hysteresis VHYS 100 mV 7
Tri-level input Hi-Z voltage VIZ 0.9 V 7
Tri-level input hysteresis VHYS 100 mV 7
Tri-level pulldown resistance RPD 180 kΩ To GND 7
Tri-level pullup resistance RPU 480 kΩ To VREG 7
Output logic low voltage VOL 0.5 V IO = 5 mA 7
High-side FET on resistance RDS(ON) 430 mΩ VDD = 5 V, I = 0.5 A, TJ = 25°C 7
Low-side FET on resistance RDS(ON) 300 mΩ VDD = 5 V, I = 0.5 A, TJ = 25°C 7
Output rise time tRISE 50 ns 7
Output fall time tFALL 50 ns 7
Output dead time tDEAD 150 ns Internal dead time 7
Externally applied VREF input current IREF 2 A VREF = 1 to 3.3 V 7
xSEN trip voltage VTRIP 500 mV For 100% current step with VREF = 3.3 V 7
Current sense amplifier gain K 6.6 V/V Reference Only 8
Current control constant off time (TOFF = GND) tOFF 20 s TOFF = GND 8
Current control constant off time (TOFF = Hi-Z) tOFF 10 s TOFF = Hi-Z 8
Current control constant off time (TOFF = VREG) tOFF 30 s TOFF = VREG 8
VDD under voltage lockout (falling) VUVLO 2.7 V VDD falling; UVLO Report 8
VDD under voltage lockout (rising) VUVLO 2.8 V VDD rising; UVLO Recovery 8
Overcurrent Protection Trip Level IOCP 2 A 8
Overcurrent Deglitch Time tOCP 0.1 s 8
Overcurrent Protection Period tRETRY 1.6 ms 8
Thermal shutdown temperature TTSD 160 °C Die Temperature TJ 8
Thermal shutdown hysteresis THYS 30 °C Die Temperature TJ 8
Junction-to-ambient thermal resistance θJA 60 °C/W 6

Materials and finish

As the datasheet states them (page.json metadata.appearance; the 3D model's colours follow it).

Part Material Colour / plating Datasheet says Page
contacts copper 4. No via in traces from IC pin VDD through C2/C1 to IC pin GND, keep the trace as short as possible; 5. Try to provide a separate short and thick power line to the device, the copper width is recomme 18

CAD (KiCad official)

  • Symbol: AW8646QNR
  • Footprint: Package_DFN_QFN:QFN-24-1EP_4x4mm_P0.5mm_EP2.7x2.7mm
  • 3D model: QFN-24-EP(4x4) (KiCad packages3D, STEP)
  • 3D model files: aw8646qnr-etched.step / aw8646qnr-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); aw8646qnr.step / aw8646qnr.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: AWINIC Shanghai Awinic Tech datasheet (23 pp, sha256 1964a5438f8c1015, retrieved 2026-10-19, tier: lcsc)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF