component
AW8623DNR
Public Made by Adomby adom
AWINIC(Shanghai Awinic Tech) Gate Drive ICs, DFN-10(3x3). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
Made with KiCad 10.0 · needs KiCad 10.0 or later to open · KiCad file format 20260206
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|---|---|
| docs | 3d ago |
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| aw8623dnr-etched.step | 3d ago |
| aw8623dnr-hero.glb | 3d ago |
| aw8623dnr-hero.overlay.json | 3d ago |
| aw8623dnr.glb | 3d ago |
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AW8623DNR
AWINIC(Shanghai Awinic Tech) · Gate Drive ICs · DFN-10(3x3)
AW8623DNR from AWINIC(Shanghai Awinic Tech), in a DFN-10(3x3). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | VREG | power_out | 1.8V regulator output, decoupled with an external capacitor. |
| 2 | HDP | output | Positive haptic driver differential output; absolute maximum -0.3V to VDD+0.3V. |
| 3 | GND | power_in | Supply ground. |
| 4 | HDN | output | Negative haptic driver differential output; absolute maximum -0.3V to VDD+0.3V. |
| 5 | VDD | power_in | Chip power supply, 3V to 5.5V operating range (absolute maximum -0.3V to 6.0V). |
| 6 | SCL | input | I2C bus clock input, supports up to 1MHz. |
| 7 | SDA | bidirectional | I2C bus data input/output. |
| 8 | RSTN | input | Active low hardware reset; when low, the chip is shut down. |
| 9 | INTN | output | Interrupt output, open drain. |
| 10 | TRIG | input | Input trigger with internal pull down. |
| 11 | EP | passive | Exposed pad (from the footprint; not named in the datasheet pin table). |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | AWINIC(Shanghai Awinic Tech) |
| Package | DFN-10(3x3) |
| Category | Power Supply Chip |
| Pins | 11 |
Electrical characteristics
Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Battery supply voltage | VDD | 3 | 5.5 | V | On pin VDD | 6 | |
| Logic input low level | VIL | 0.5 | V | RSTN/TRIG/SCLK | 6 | ||
| Logic input high level | VIH | 1.3 | V | RSTN/TRIG/SCLK | 6 | ||
| Logic output low level | VOL | 0.4 | V | INTN/SDA, IOUT=4mA | 6 | ||
| Logic output high level | VOH | 1.3 | V | INTN/SDA, IOUT=-4mA | 6 | ||
| Output offset voltage | VOS | -30 | 0 | 30 | mV | I2C signal input 0 | 6 |
| Shutdown current | ISD | 0.5 | 1 | μA | VDD=4.2V, RSTN =0V | 6 | |
| Standby current | ISTBY | 10 | μA | VDD=3.6V, RSTN=SCL=SDA=1.8V | 6 | ||
| PWM Output Frequency | Fo(PWM) | -2.5 | 24 | 2.5 | kHz | VDD=3V to 5.5V; tolerance in % | 6 |
| Voltage at VREG pin | VREG | 1.8 | V | 6 | |||
| Quiescent current | IQ | 1 | mA | VDD=3.6V | 6 | ||
| Under-voltage protection voltage | UVP | 2.7 | V | 6 | |||
| Under-voltage protection hysteresis voltage | 100 | mV | 6 | ||||
| Over temperature protection threshold | TSD | 160 | °C | 6 | |||
| Over temperature protection recovery threshold | TSDR | 130 | °C | 6 | |||
| Waveform startup time | TSTART | 0.4 | ms | From trigger to output signal | 6 | ||
| Drain-Source on-state resistance | Rdson | 400 | mΩ | Include NMOS and PMOS | 6 | ||
| Load impedance threshold for over current protection | Rocp | 2 | Ω | VDD=3.6V | 6 | ||
| Output voltage | Vpeak | 3.6 | V | RL=8Ω+100μH,VDD=4.2V | 6 | ||
| Output voltage | Vpeak | 3.8 | V | RL=16Ω+100μH,VDD=4.2V | 6 | ||
| Battery Supply Voltage VDD | VDD | -0.3 | 6 | V | 5 | ||
| HDP, HDN voltage | HDP, HDN | -0.3 | V | -0.3V to VDD+0.3V | 5 | ||
| Minimum load resistance | RL | 5 | Ω | 5 | |||
| Ambient Temperature Range | -40 | 85 | °C | 5 | |||
| Maximum Junction Temperature | TJMAX | 165 | °C | 5 | |||
| Storage Temperature Range | TSTG | -65 | 150 | °C | 5 | ||
| Lead Temperature | 260 | °C | Soldering 10 Seconds | 5 | |||
| ESD HBM | HBM | -2000 | 2000 | V | Human Body Model | 5 | |
| ESD CDM | CDM | -1500 | 1500 | V | Charge Device Model | 5 | |
| Package Thermal Resistance | θJA | 60 | °C/W | 5 | |||
| SCL Clock frequency | fSCL | 1000 | kHz | Super-fast mode | 7 | ||
| SCL Low level Duration | tLOW | 0.5 | μs | Super-fast mode | 7 | ||
| SCL High level Duration | tHIGH | 0.3 | μs | Super-fast mode | 7 | ||
| SCL, SDA rise time | tRISE | 0.1 | μs | Super-fast mode | 7 | ||
| SCL, SDA fall time | tFALL | 0.1 | μs | Super-fast mode | 7 | ||
| Setup time SCL to START state | tSU:STA | 0.3 | μs | Super-fast mode | 7 | ||
| Start condition hold time | tHD:STA | 0.3 | μs | Super-fast mode, Repeat-start | 7 | ||
| Stop condition setup time | tSU:STO | 0.3 | μs | Super-fast mode | 7 | ||
| Bus idle time START state to STOP state | tBUF | 0.5 | μs | Super-fast mode | 7 | ||
| SDA setup time | tSU:DAT | 0.1 | μs | Super-fast mode | 7 | ||
| SDA hold time | tHD:DAT | 10 | ns | Super-fast mode | 7 |
CAD (KiCad official)
- Symbol:
AW8623DNR - Footprint:
Package_DFN_QFN:DFN-10-1EP_3x3mm_P0.5mm_EP1.55x2.48mm - 3D model: DFN-10(3x3) (KiCad packages3D, STEP)
- 3D model files:
aw8623dnr-etched.step/aw8623dnr-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);aw8623dnr.step/aw8623dnr.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: AWINIC(Shanghai Awinic Tech) datasheet (44 pp, sha256
ba313512e765c14e, retrieved 2026-10-23, tier: lcsc) - Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-sonnet-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).