component
AW37103D330DNR
Public Made by Adomby adom
AWINIC Shanghai Awinic Tech Voltage Regulators - Linear, Low Drop Out (LDO) Regulators, DFN1x1-4L. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
3D Model
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Symbol & Footprint
Schematic Symbol
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PCB Footprint
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Datasheet
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Contents
README
markdownAW37103D330DNR
AWINIC Shanghai Awinic Tech · Voltage Regulators - Linear, Low Drop Out (LDO) Regulators · DFN1x1-4L
AW37103D330DNR from AWINIC Shanghai Awinic Tech, in a DFN1x1-4L. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | OUT | power_out | Regulated output voltage pin; place a 1µF or more ceramic capacitor at the output pin. |
| 2 | GND | power_in | Ground pin. |
| 3 | CE | input | Chip enable pin (high active) with a built-in 30nA pull-down; the device is enabled above 1V and disabled below 0.4V. |
| 4 | IN | power_in | Input supply pin, rated 1.2V to 5.5V; place a 1µF or more bypass capacitor at the supply. |
| 5 | EXP | passive | Exposed pad should be tied to the ground plane for better power dissipation. |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | AWINIC Shanghai Awinic Tech |
| Package | DFN1x1-4L |
| Category | Power Management (PMIC) |
| Pins | 5 |
Electrical characteristics
Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Input Voltage Range | VIN | 1.2 | 5.5 | V | 8 | ||
| Output Voltage Accuracy | VOUT_ACC | -2 | 2 | % | TA=25°C, IOUT=1mA | 8 | |
| Load Regulation | LOADReg | 0.5 | % | 1mA≤IOUT≤300mA | 8 | ||
| Line Regulation | LINEReg | 1 | mV | VOUT(SET)+0.5V≤VIN≤5.5V, IOUT=1mA | 8 | ||
| Dropout Voltage | Vdropout | 179 | mV | IOUT=300mA, VOUT(SET)=3.3V | 8 | ||
| Shutdown Current | ISD | 0.1 | 1 | μA | VCE<0.4V | 8 | |
| Quiescent Current | IQ | 2 | 4 | μA | IOUT=0mA | 8 | |
| CE Input Voltage High | VCEH | 1 | V | -40°C ≤TA≤85°C | 8 | ||
| CE Input Voltage Low | VCEL | 0.4 | V | -40°C ≤TA≤85°C | 8 | ||
| Output Voltage Noise | VN | 90 | Vrms | IOUT=30mA, BW=10Hz to 100kHz, VOUT(SET)=3.3V | 8 | ||
| Output Current Limit | ICL | 300 | mA | VOUT=90%*VOUT(SET) | 8 | ||
| Short Current Limit | ISC | 300 | mA | VOUT<10%*VOUT(SET) | 8 | ||
| Output Voltage Temperature Coefficient | VTC | -100 | 100 | ppm/°C | -40°C ≤TA≤85°C | 8 | |
| Auto Discharge Resistance | RDISC | 80 | Ω | VIN=4.3V, VCE<0.4V | 8 | ||
| CE Pull Down Current | ICE | 30 | nA | 8 | |||
| Thermal Shutdown Threshold Temperature | TSDH | 155 | °C | Temperature rising | 8 | ||
| Thermal Shutdown Reset Threshold Temperature | TSDL | 130 | °C | Temperature falling | 8 | ||
| Recommended Operating Junction Temperature | TJREC | -40 | 125 | °C | 7 | ||
| Operating Free-Air Temperature Range | TA | -40 | 85 | °C | 7 | ||
| Input Capacitor CIN (recommended minimum) | CIN | 1 | μF | IN pin, X5R or X7R ceramic | 5 | ||
| Output Capacitor COUT (recommended minimum) | COUT | 1 | μF | OUT pin, X5R or X7R ceramic | 5 | ||
| Effective Output Capacitance | COUT | 0.7 | μF | Over full range of operating conditions | 5 | ||
| Input Voltage Range (absolute maximum) | VIN | -0.3 | 6.5 | V | 7 | ||
| Enable Control Voltage Range | VCE | -0.3 | 6.5 | V | 7 | ||
| Output Voltage Range (-0.3V to VIN+0.3V, max 6.5V) | VOUT | -0.3 | 6.5 | V | 7 | ||
| Maximum Operating Junction Temperature | TJMAX | 150 | °C | 7 | |||
| Storage Temperature | TSTG | -65 | 150 | °C | 7 | ||
| Lead Temperature | 260 | °C | Soldering 10 seconds | 7 | |||
| Junction-to-Ambient Thermal Resistance DFN1*1-4L | θJA | 232 | °C/W | JEDEC 2S2P | 7 | ||
| ESD HBM | -2 | 2 | kV | ESDA/JEDEC JS-001-2017 | 7 | ||
| ESD CDM | -1.5 | 1.5 | kV | ESDA/JEDEC JS-002-2018 | 7 | ||
| Latch-Up Positive Current Injection | +IT | 200 | mA | JESD78E | 7 | ||
| Latch-Up Negative Current Injection | -IT | -200 | mA | JESD78E | 7 |
Materials and finish
As the datasheet states them (page.json metadata.appearance; the 3D model's colours follow it).
| Part | Material | Colour / plating | Datasheet says | Page |
|---|---|---|---|---|
| contacts | copper | to IN and OUT pins respectively. Avoid connecting device and chip pins with two different layers of copper, | 19 |
CAD (KiCad official)
- Symbol:
AW37103D330DNR - Footprint:
Package_DFN_QFN:UDFN-4-1EP_1x1mm_P0.65mm_EP0.48x0.48mm - 3D model: DFN1x1-4L (KiCad packages3D, STEP)
- 3D model files:
aw37103d330dnr-etched.step/aw37103d330dnr-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);aw37103d330dnr.step/aw37103d330dnr.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: AWINIC Shanghai Awinic Tech datasheet (28 pp, sha256
10a94e23b5abc7d4, retrieved 2026-10-18, tier: lcsc) - Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-haiku-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).