component
AW37103D280DNR
Public Made by Adomby adom
AWINIC Shanghai Awinic Tech Voltage Regulators - Linear, Low Drop Out (LDO) Regulators, DFN1x1-4L. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
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AW37103D280DNR
AWINIC Shanghai Awinic Tech · Voltage Regulators - Linear, Low Drop Out (LDO) Regulators · DFN1x1-4L
AW37103D280DNR from AWINIC Shanghai Awinic Tech, in a DFN1x1-4L. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | OUT | power_out | Regulated output voltage pin; a 1μF or more ceramic capacitor should be placed at the output pin. |
| 2 | GND | power_in | Ground reference pin. |
| 3 | CE | input | Chip enable pin, high active: above 1V enables the regulator and below 0.4V disables it, with a built-in 30nA pull-down current to ground. |
| 4 | IN | power_in | Input supply pin, rated for 1.2V to 5.5V; a 1μF or more bypass capacitor should be placed at the supply pin. |
| 5 | EXP | passive | Exposed pad should be tied to the ground plane for better power dissipation. |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | AWINIC Shanghai Awinic Tech |
| Package | DFN1x1-4L |
| Category | Power Management (PMIC) |
| Pins | 5 |
Electrical characteristics
Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Input Voltage Range | VIN | 1.2 | 5.5 | V | 10 | ||
| Output Voltage Accuracy | VOUT_ACC | -2 | 2 | % | TA=25°C, IOUT=1mA | 10 | |
| Shutdown Current | ISD | 0.1 | 1 | μA | VCE<0.4V | 10 | |
| Quiescent Current | IQ | 2 | 4 | μA | IOUT=0mA | 10 | |
| CE Input Voltage High | VCEH | 1 | V | -40°C ≤ TA ≤ 85°C | 10 | ||
| CE Input Voltage Low | VCEL | 0.4 | V | -40°C ≤ TA ≤ 85°C | 10 | ||
| Output Voltage Temperature Coefficient | VTC | -100 | 100 | ppm/°C | -40°C ≤ TA ≤ 85°C | 10 | |
| Input Voltage | -0.3 | 6.5 | V | 9 | |||
| Enable Control Voltage Range | -0.3 | 6.5 | V | 9 | |||
| Output Voltage Range | -0.3 | 6.5 | V | Upper bound VIN+0.3V; max. 6.5V | 9 | ||
| Maximum Operating Junction Temperature | TJMAX | 150 | °C | 9 | |||
| Storage Temperature | TSTG | -65 | 150 | °C | 9 | ||
| Lead Temperature (soldering) | 260 | °C | 10 seconds soldering | 9 | |||
| ESD HBM (Human Body Model) | -2 | 2 | kV | All pins, ESDA/JEDEC JS-001-2017 | 9 | ||
| ESD CDM (Charged Device Model) | -1.5 | 1.5 | kV | All pins, ESDA/JEDEC JS-002-2018 | 9 | ||
| Latch-Up +IT | 200 | mA | JESD78E | 9 | |||
| Latch-Up -IT | -200 | mA | JESD78E | 9 | |||
| Recommended Operating Junction Temperature | TJREC | -40 | 125 | °C | 9 | ||
| Operating Free-Air Temperature Range | -40 | 85 | °C | 9 | |||
| Load Regulation | LOADReg | 0.5 | % | 1mA≤IOUT≤300mA | 10 | ||
| Line Regulation | LINEReg | 1 | mV | VOUT(SET)+0.5V≤VIN≤5.5V, IOUT=1mA | 10 | ||
| Dropout Voltage | Vdropout | 203 | mV | IOUT=300mA, VOUT(SET)=2.8V | 10 | ||
| Output Voltage Noise | VN | 80 | Vrms | IOUT=30mA, BW=10Hz to 100kHz, VOUT(SET)=2.8V | 10 | ||
| Output Current Limit | ICL | 300 | mA | VOUT=90%*VOUT(SET) | 10 | ||
| Short Current Limit | ISC | 300 | mA | VOUT<10%*VOUT(SET) | 10 | ||
| Auto Discharge Resistance | RDISC | 80 | Ω | VIN=4.3V, VCE<0.4V | 10 | ||
| CE Pull Down Current | ICE | 30 | nA | 10 | |||
| Thermal Shutdown Threshold Temperature (rising) | TSDH | 155 | °C | Temperature rising | 10 | ||
| Thermal Shutdown Reset Threshold Temperature (falling) | TSDL | 130 | °C | Temperature falling | 10 | ||
| Junction-to-Ambient Thermal Resistance | θJA | 232 | °C/W | DFN1*1-4L, JEDEC 2S2P | 9 |
Materials and finish
As the datasheet states them (page.json metadata.appearance; the 3D model's colours follow it).
| Part | Material | Colour / plating | Datasheet says | Page |
|---|---|---|---|---|
| contacts | copper | to IN and OUT pins respectively. Avoid connecting device and chip pins with two different layers of copper, | 22 |
CAD (KiCad official)
- Symbol:
AW37103D280DNR - Footprint:
Package_DFN_QFN:UDFN-4-1EP_1x1mm_P0.65mm_EP0.48x0.48mm - 3D model: DFN1x1-4L (KiCad packages3D, STEP)
- 3D model files:
aw37103d280dnr-etched.step/aw37103d280dnr-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);aw37103d280dnr.step/aw37103d280dnr.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: AWINIC Shanghai Awinic Tech datasheet (31 pp, sha256
5bd9885b0c60ed56, retrieved 2026-10-18, tier: lcsc) - Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-haiku-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).
# AW37103D280DNR
**AWINIC Shanghai Awinic Tech** · Voltage Regulators - Linear, Low Drop Out (LDO) Regulators · DFN1x1-4L
AW37103D280DNR from AWINIC Shanghai Awinic Tech, in a DFN1x1-4L. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
## Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | OUT | power_out | Regulated output voltage pin; a 1μF or more ceramic capacitor should be placed at the output pin. |
| 2 | GND | power_in | Ground reference pin. |
| 3 | CE | input | Chip enable pin, high active: above 1V enables the regulator and below 0.4V disables it, with a built-in 30nA pull-down current to ground. |
| 4 | IN | power_in | Input supply pin, rated for 1.2V to 5.5V; a 1μF or more bypass capacitor should be placed at the supply pin. |
| 5 | EXP | passive | Exposed pad should be tied to the ground plane for better power dissipation. |
## Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | AWINIC Shanghai Awinic Tech |
| Package | DFN1x1-4L |
| Category | Power Management (PMIC) |
| Pins | 5 |
## Electrical characteristics
Limits as printed in the datasheet (page.json `metadata.characteristics` carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Input Voltage Range | VIN | 1.2 | | 5.5 | V | | 10 |
| Output Voltage Accuracy | VOUT_ACC | -2 | | 2 | % | TA=25°C, IOUT=1mA | 10 |
| Shutdown Current | ISD | | 0.1 | 1 | μA | VCE<0.4V | 10 |
| Quiescent Current | IQ | | 2 | 4 | μA | IOUT=0mA | 10 |
| CE Input Voltage High | VCEH | 1 | | | V | -40°C ≤ TA ≤ 85°C | 10 |
| CE Input Voltage Low | VCEL | | | 0.4 | V | -40°C ≤ TA ≤ 85°C | 10 |
| Output Voltage Temperature Coefficient | VTC | -100 | | 100 | ppm/°C | -40°C ≤ TA ≤ 85°C | 10 |
| Input Voltage | | -0.3 | | 6.5 | V | | 9 |
| Enable Control Voltage Range | | -0.3 | | 6.5 | V | | 9 |
| Output Voltage Range | | -0.3 | | 6.5 | V | Upper bound VIN+0.3V; max. 6.5V | 9 |
| Maximum Operating Junction Temperature | TJMAX | | | 150 | °C | | 9 |
| Storage Temperature | TSTG | -65 | | 150 | °C | | 9 |
| Lead Temperature (soldering) | | | | 260 | °C | 10 seconds soldering | 9 |
| ESD HBM (Human Body Model) | | -2 | | 2 | kV | All pins, ESDA/JEDEC JS-001-2017 | 9 |
| ESD CDM (Charged Device Model) | | -1.5 | | 1.5 | kV | All pins, ESDA/JEDEC JS-002-2018 | 9 |
| Latch-Up +IT | | | | 200 | mA | JESD78E | 9 |
| Latch-Up -IT | | -200 | | | mA | JESD78E | 9 |
| Recommended Operating Junction Temperature | TJREC | -40 | | 125 | °C | | 9 |
| Operating Free-Air Temperature Range | | -40 | | 85 | °C | | 9 |
| Load Regulation | LOADReg | | 0.5 | | % | 1mA≤IOUT≤300mA | 10 |
| Line Regulation | LINEReg | | 1 | | mV | VOUT(SET)+0.5V≤VIN≤5.5V, IOUT=1mA | 10 |
| Dropout Voltage | Vdropout | | 203 | | mV | IOUT=300mA, VOUT(SET)=2.8V | 10 |
| Output Voltage Noise | VN | | 80 | | Vrms | IOUT=30mA, BW=10Hz to 100kHz, VOUT(SET)=2.8V | 10 |
| Output Current Limit | ICL | | 300 | | mA | VOUT=90%*VOUT(SET) | 10 |
| Short Current Limit | ISC | | 300 | | mA | VOUT<10%*VOUT(SET) | 10 |
| Auto Discharge Resistance | RDISC | | 80 | | Ω | VIN=4.3V, VCE<0.4V | 10 |
| CE Pull Down Current | ICE | | 30 | | nA | | 10 |
| Thermal Shutdown Threshold Temperature (rising) | TSDH | | 155 | | °C | Temperature rising | 10 |
| Thermal Shutdown Reset Threshold Temperature (falling) | TSDL | | 130 | | °C | Temperature falling | 10 |
| Junction-to-Ambient Thermal Resistance | θJA | | 232 | | °C/W | DFN1*1-4L, JEDEC 2S2P | 9 |
## Materials and finish
As the datasheet states them (page.json `metadata.appearance`; the 3D model's colours follow it).
| Part | Material | Colour / plating | Datasheet says | Page |
|---|---|---|---|---|
| contacts | copper | | to IN and OUT pins respectively. Avoid connecting device and chip pins with two different layers of copper, | 22 |
## CAD (KiCad official)
- Symbol: `AW37103D280DNR`
- Footprint: `Package_DFN_QFN:UDFN-4-1EP_1x1mm_P0.65mm_EP0.48x0.48mm`
- 3D model: DFN1x1-4L (KiCad packages3D, STEP)
- 3D model files: `aw37103d280dnr-etched.step` / `aw37103d280dnr-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `aw37103d280dnr.step` / `aw37103d280dnr.glb` are the bare package body.
## Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- **Datasheet:** [AWINIC Shanghai Awinic Tech datasheet](https://jlcpcb.com/api/file/downloadByFileSystemAccessId/8589835684778577920) (31 pp, sha256 `5bd9885b0c60ed56`, retrieved 2026-10-18, tier: lcsc)
- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.3`, primary `claude-haiku-5-5` (text), consensus `claude-sonnet-5-5` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
- **CAD:** KiCad official libraries (CC-BY-SA 4.0).
[Datasheet PDF](docs/aw37103d280dnr-datasheet.pdf)