# AW37050D330DNR

**AWINIC Shanghai Awinic Tech** · Voltage Regulators - Linear, Low Drop Out (LDO) Regulators · DFN1x1-4L

AW37050D330DNR from AWINIC Shanghai Awinic Tech, in a DFN1x1-4L. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

## Pinout

| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | OUT | power_out | Regulated output voltage pin; the datasheet says to place a 1µF or larger ceramic capacitor at this pin. |
| 2 | GND | power_in | Ground pin. |
| 3 | CE | input | Active-high chip enable: the regulator is disabled below 0.4V and enabled above 1V, with a built-in 140nA pull-down to ground, so CE can be tied to IN if enable is not used. |
| 4 | IN | power_in | Input supply pin with a 1.4V to 5.5V input range; the datasheet says to place a 1µF or larger bypass capacitor at this pin. |
| 5 | EXP | passive | Exposed pad should be tied to the ground plane for better power dissipation. |

## Key specifications

| Parameter | Value |
|---|---|
| Manufacturer | AWINIC Shanghai Awinic Tech |
| Package | DFN1x1-4L |
| Category | Power Management (PMIC) |
| Pins | 5 |

## Electrical characteristics

Limits as printed in the datasheet (page.json `metadata.characteristics` carries them as data).

| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Input Voltage Range | VIN | 1.4 |  | 5.5 | V |  | 7 |
| Output Voltage Accuracy | VOUT_ACC | -1 |  | 1 | % | TA=25°C | 7 |
| Output Voltage Accuracy | VOUT_ACC | -2 |  | 2 | % | -40°C ≤TA≤85°C | 7 |
| Load Regulation | LOADReg |  | 5 | 30 | mV | 1mA≤IOUT≤500mA | 7 |
| Line Regulation | LINEReg |  | 1 | 5 | mV | VOUT(SET)+0.5V≤VIN ≤5.5V | 7 |
| Dropout Voltage (VOUT(SET)=3.3V) | Vdropout |  | 275 |  | mV | IOUT=500mA, when VOUT falls 100mV below VOUT(SET) | 7 |
| Shutdown Current | ISD |  | 0.1 | 1 | μA | VCE<0.4V | 7 |
| Quiescent Current | IQ |  | 50 | 100 | μA | IOUT=0mA | 7 |
| CE Input Voltage High | VCEH | 1 |  |  | V | -40°C ≤TA≤85°C | 7 |
| CE Input Voltage Low | VCEL |  |  | 0.4 | V | -40°C ≤TA≤85°C | 7 |
| Output Current Limit | ICL |  | 500 |  | mA | VOUT=90%*VOUT(SET) | 7 |
| Short Current Limit | ISC |  | 150 |  | mA | VOUT<10%*VOUT(SET) | 7 |
| Output Voltage Temperature Coefficient | VTC | -40 |  | 40 | ppm/°C | -40°C ≤TA≤85°C | 7 |
| Auto Discharge Resistance | RDISC |  | 130 |  | Ω | VIN=4V, VCE<0.4V, VOUT=2.8V | 7 |
| CE Pull Down Current | ICE |  | 140 |  | nA |  | 7 |
| Thermal Shutdown Threshold | TSDH |  | 160 |  | °C | Temperature rising | 7 |
| Thermal Shutdown Reset Threshold | TSDL |  | 130 |  | °C | Temperature falling | 7 |
| Input Voltage (absolute maximum) |  | -0.3 |  | 6.5 | V |  | 6 |
| Enable Control Voltage (absolute maximum) |  | -0.3 |  | 6.5 | V |  | 6 |
| Output Voltage (absolute maximum) |  | -0.3 |  | 6.5 | V | max. 6.5V; upper bound VIN+0.3V | 6 |
| Maximum Operating Junction Temperature | TJ_MAX |  |  | 150 | °C |  | 6 |
| Storage Temperature | TSTG | -65 |  | 150 | °C |  | 6 |
| Lead Temperature |  |  |  | 260 | °C | Soldering 10 seconds | 6 |
| ESD HBM |  | -2 |  | 2 | kV | All pins, ESDA/JEDEC JS-001-2017 | 6 |
| ESD CDM |  | -1.5 |  | 1.5 | kV | All pins, ESDA/JEDEC JS-002-2018 | 6 |
| Latch-Up |  | -200 |  | 200 | mA | JESD78E | 6 |
| Recommended Operating Junction Temperature | TJ_REC | -40 |  | 125 | °C |  | 6 |
| Operating Free-Air Temperature | TA | -40 |  | 85 | °C |  | 6 |
| Maximum Power Consumption (DFN 1mmX1mm-4L) |  |  |  | 464 | mW | TA=25°C, TJ_REC=125°C | 6 |
| Junction-to-Ambient Thermal Resistance (DFN) | RθJA |  | 215.4 |  | °C/W | JEDEC 2S2P | 6 |
| Junction-to-Case (Top) Thermal Resistance (DFN) | RθJC(top) |  | 161.85 |  | °C/W |  | 6 |
| Junction-to-Board Thermal Resistance (DFN) | RθJB |  | 156.4 |  | °C/W |  | 6 |
| Junction-to-Top Characterization Parameter (DFN) | ψJT |  | 17.3 |  | °C/W |  | 6 |
| Junction-to-Board Characterization Parameter (DFN) | ψJB |  | 170.4 |  | °C/W |  | 6 |
| Junction-to-Case (Bottom) Thermal Resistance (DFN) | RθJC(bot) |  | 118 |  | °C/W |  | 6 |

## Materials and finish

As the datasheet states them (page.json `metadata.appearance`; the 3D model's colours follow it).

| Part | Material | Colour / plating | Datasheet says | Page |
|---|---|---|---|---|
| contacts | copper |  | to IN and OUT pins respectively. Avoid connecting device and chip pins with two different layers of copper, | 17 |

## CAD (KiCad official)

- Symbol: `AW37050D330DNR`
- Footprint: `Package_DFN_QFN:UDFN-4-1EP_1x1mm_P0.65mm_EP0.48x0.48mm`
- 3D model: DFN1x1-4L (KiCad packages3D, STEP)
- 3D model files: `aw37050d330dnr-etched.step` / `aw37050d330dnr-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `aw37050d330dnr.step` / `aw37050d330dnr.glb` are the bare package body.

## Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

- **Datasheet:** [AWINIC Shanghai Awinic Tech datasheet](https://jlcpcb.com/api/file/downloadByFileSystemAccessId/8590454918332256256) (26 pp, sha256 `a27998cbab32dc9b`, retrieved 2026-10-18, tier: lcsc)
- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.3`, primary `claude-haiku-5-5` (text), consensus `claude-sonnet-5-5` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
- **CAD:** KiCad official libraries (CC-BY-SA 4.0).

[Datasheet PDF](docs/aw37050d330dnr-datasheet.pdf)