component
AW37030D285DNR
Public Made by Adomby adom
AWINIC(Shanghai Awinic Tech) Linear Voltage Regulators (LDO), DFN1x1-4L. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
3D Model
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Symbol & Footprint
Schematic Symbol
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PCB Footprint
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Datasheet
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Contents
README
markdownAW37030D285DNR
AWINIC(Shanghai Awinic Tech) · Linear Voltage Regulators (LDO) · DFN1x1-4L
AW37030D285DNR from AWINIC(Shanghai Awinic Tech), in a DFN1x1-4L. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | OUT | power_out | Regulated output voltage pin; put a 1µF or more ceramic capacitor at the output pin. |
| 2 | GND | power_in | Ground. |
| 3 | CE | input | Chip enable pin, active high, with built-in 140nA pull-down current; below 0.4V disables, above 1V enables. |
| 4 | IN | power_in | Input supply pin (1.4V to 5.5V); put a 1µF or more bypass capacitor at the power supply. |
| 5 | EXP | passive | Exposed pad should be tied to ground plane for better power dissipation. |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | AWINIC(Shanghai Awinic Tech) |
| Package | DFN1x1-4L |
| Category | Power Supply Chip |
| Pins | 5 |
Electrical characteristics
Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Output Voltage Accuracy | VOUT_ACC | -1 | 1 | % | TA=25°C | 8 | |
| Output Voltage Accuracy | VOUT_ACC | -2 | 2 | % | -40°C ≤TA≤85°C | 8 | |
| Input Voltage Range | VIN | 1.4 | 5.5 | V | 8 | ||
| Load Regulation | LOADReg | 1 | 20 | mV | 1mA≤IOUT≤300mA | 8 | |
| Line Regulation | LINEReg | 1 | 5 | mV | VOUT(SET)+0.5V≤VIN ≤5.5V | 8 | |
| Shutdown Current | ISD | 0.1 | 1 | A | VCE<0.4V | 8 | |
| Quiescent Current | IQ | 50 | 100 | A | IOUT=0mA | 8 | |
| CE Input Voltage H | VCEH | 1 | V | -40°C ≤TA≤85°C | 8 | ||
| CE Input Voltage L | VCEL | 0.4 | V | -40°C ≤TA≤85°C | 8 | ||
| Output Voltage Temperature Coefficient | VTC | -40 | 40 | ppm/°C | -40°C ≤TA≤85°C | 8 | |
| Output Current Limit | ICL | 300 | mA | VOUT=90%*VOUT(SET) | 8 | ||
| Short Current Limit | ISC | 120 | mA | VOUT<10%*VOUT(SET) | 8 | ||
| Auto Discharge Resistance | RDISC | 130 | Ω | VIN=4V, VCE<0.4V, VOUT=2.8V | 8 | ||
| CE Pull Down Current | ICE | 140 | nA | 8 | |||
| Thermal Shutdown Threshold | TSDH | 160 | °C | Temperature Rising | 8 | ||
| Thermal Shutdown Reset Threshold | TSDL | 130 | °C | Temperature Falling | 8 | ||
| Input voltage range | VIN | -0.3 | 6.5 | V | 7 | ||
| Enable control voltage range | VCE | -0.3 | 6.5 | V | 7 | ||
| Output voltage range | VOUT | -0.3 | 6.5 | V | -0.3V to VIN+0.3V, max. 6.5V | 7 | |
| Maximum operating junction temperature | TJ_MAX | 150 | °C | 7 | |||
| Recommended operating junction temperature | TJ_REC | -40 | 125 | °C | 7 | ||
| Operating free-air temperature range | -40 | 85 | °C | 7 | |||
| Storage temperature | TSTG | -65 | 150 | °C | 7 | ||
| Lead temperature | 260 | °C | soldering 10 seconds | 7 | |||
| Maximum power consumption | 464 | mW | DFN 1mmX1mm-4L, TA=25°C, TJ_REC=125°C | 7 | |||
| ESD HBM | -2 | 2 | kV | All pins, ESDA/JEDEC JS-001-2017 | 7 | ||
| ESD CDM | -1.5 | 1.5 | kV | All pins, ESDA/JEDEC JS-002-2018 | 7 | ||
| Latch-Up | IT | -200 | 200 | mA | JESD78E | 7 | |
| Junction-to-ambient thermal resistance | RθJA | 215.4 | °C/W | DFN 1mmX1mm-4L, JEDEC 2S2P | 7 | ||
| Junction-to-case(top) thermal resistance | RθJC(top) | 161.85 | °C/W | DFN 1mmX1mm-4L | 7 | ||
| Junction-to-board thermal resistance | RθJB | 156.4 | °C/W | DFN 1mmX1mm-4L | 7 | ||
| Junction-to-top characterization parameter | ψJT | 17.3 | °C/W | DFN 1mmX1mm-4L | 7 | ||
| Junction-to-board characterization parameter | ψJB | 170.4 | °C/W | DFN 1mmX1mm-4L | 7 | ||
| Junction-to-case(bottom) thermal resistance | RθJC(bot) | 118 | °C/W | DFN 1mmX1mm-4L | 7 |
Materials and finish
As the datasheet states them (page.json metadata.appearance; the 3D model's colours follow it).
| Part | Material | Colour / plating | Datasheet says | Page |
|---|---|---|---|---|
| contacts | copper | to IN and OUT pins respectively. Avoid connecting device and chip pins with two different layers of copper, | 18 |
CAD (KiCad official)
- Symbol:
AW37030D285DNR - Footprint:
Package_DFN_QFN:UDFN-4-1EP_1x1mm_P0.65mm_EP0.48x0.48mm - 3D model: DFN1x1-4L (KiCad packages3D, STEP)
- 3D model files:
aw37030d285dnr-etched.step/aw37030d285dnr-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);aw37030d285dnr.step/aw37030d285dnr.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: AWINIC(Shanghai Awinic Tech) datasheet (27 pp, sha256
1e6900a279a56b96, retrieved 2026-10-22, tier: lcsc) - Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-sonnet-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).