# AW37030D280DNR

**AWINIC Shanghai Awinic Tech** · Voltage Regulators - Linear, Low Drop Out (LDO) Regulators · DFN1x1-4L

AW37030D280DNR from AWINIC Shanghai Awinic Tech, in a DFN1x1-4L. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

## Pinout

| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | OUT | power_out | Regulated output voltage pin; a 1μF or more ceramic capacitor should be placed at the output pin. |
| 2 | GND | power_in | Ground pin. |
| 3 | CE | input | Chip enable pin (high active) with a built-in 140nA pull-down current; the regulator is enabled above 1V and disabled below 0.4V. |
| 4 | IN | power_in | Input supply pin with a 1.4V to 5.5V input range; a 1μF or more bypass capacitor should be placed at the supply. |
| 5 | EXP | passive | Exposed pad should be tied to the ground plane for better power dissipation. |

## Key specifications

| Parameter | Value |
|---|---|
| Manufacturer | AWINIC Shanghai Awinic Tech |
| Package | DFN1x1-4L |
| Category | Power Management (PMIC) |
| Pins | 5 |

## Electrical characteristics

Limits as printed in the datasheet (page.json `metadata.characteristics` carries them as data).

| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Input voltage range | VIN | 1.4 |  | 5.5 | V |  | 8 |
| Output voltage accuracy | VOUT_ACC | -1 |  | 1 | % | TA=25°C | 8 |
| Output voltage accuracy | VOUT_ACC | -2 |  | 2 | % | -40°C ≤TA≤85°C | 8 |
| Load regulation | LOADReg |  | 1 | 20 | mV | 1mA≤IOUT≤300mA | 8 |
| Line regulation | LINEReg |  | 1 | 5 | mV | VOUT(SET)+0.5V≤VIN ≤5.5V | 8 |
| Dropout voltage | Vdropout |  | 184 | 239 | mV | IOUT=300mA, when VOUT falls 100mV below VOUT(SET), VOUT(SET)=2.8V | 8 |
| Shutdown current | ISD |  | 0.1 | 1 | µA | VCE<0.4V | 8 |
| Quiescent current | IQ |  | 50 | 100 | µA | IOUT=0mA | 8 |
| CE input voltage H | VCEH | 1 |  |  | V | -40°C ≤TA≤85°C | 8 |
| CE input voltage L | VCEL |  |  | 0.4 | V | -40°C ≤TA≤85°C | 8 |
| Output current limit | ICL | 300 |  |  | mA | VOUT=90%*VOUT(SET) | 8 |
| Short current limit | ISC |  | 120 |  | mA | VOUT<10%*VOUT(SET) | 8 |
| Output voltage temperature coefficient | VTC | -40 |  | 40 | ppm/°C | -40°C ≤TA≤85°C | 8 |
| Auto discharge resistance | RDISC |  | 130 |  | Ω | VIN=4V, VCE<0.4V, VOUT=2.8V | 8 |
| CE pull down current | ICE |  | 140 |  | nA |  | 8 |
| Thermal shutdown threshold temperature | TSDH |  | 160 |  | °C | Temperature rising | 8 |
| Thermal shutdown reset threshold temperature | TSDL |  | 130 |  | °C | Temperature falling | 8 |
| Input voltage range | VIN | -0.3 |  | 6.5 | V |  | 7 |
| Enable control voltage range |  | -0.3 |  | 6.5 | V |  | 7 |
| Output voltage range |  | -0.3 |  | 6.5 | V | Upper limit VIN+0.3V, max. 6.5V | 7 |
| Maximum operating junction temperature | TJ_MAX |  |  | 150 | °C |  | 7 |
| Storage temperature | TSTG | -65 |  | 150 | °C |  | 7 |
| Lead temperature |  |  |  | 260 | °C | Soldering 10 seconds | 7 |
| ESD HBM |  | -2 |  | 2 | kV | All pins, ESDA/JEDEC JS-001-2017 | 7 |
| ESD CDM |  | -1.5 |  | 1.5 | kV | All pins, ESDA/JEDEC JS-002-2018 | 7 |
| Latch-up positive trigger current | +IT |  |  | 200 | mA | JESD78E | 7 |
| Latch-up negative trigger current | -IT | -200 |  |  | mA | JESD78E | 7 |
| Maximum power consumption (DFN 1mmX1mm-4L) |  |  |  | 464 | mW | TA=25°C, TJ_REC=125°C | 7 |
| Recommended operating junction temperature | TJ_REC | -40 |  | 125 | °C |  | 7 |
| Operating free-air temperature range |  | -40 |  | 85 | °C |  | 7 |
| Junction-to-ambient thermal resistance | RθJA |  | 215.4 |  | °C/W | DFN 1mmX1mm-4L, JEDEC 2S2P (NOTE2) | 7 |
| Junction-to-case(top) thermal resistance | RθJC(top) |  | 161.85 |  | °C/W | DFN 1mmX1mm-4L, SEMI G43-87 (NOTE2) | 7 |
| Junction-to-board thermal resistance | RθJB |  | 156.4 |  | °C/W | DFN 1mmX1mm-4L, JEDEC 2S2P (NOTE2) | 7 |
| Junction-to-top characterization parameter | ψJT |  | 17.3 |  | °C/W | DFN 1mmX1mm-4L (NOTE2) | 7 |
| Junction-to-board characterization parameter | ψJB |  | 170.4 |  | °C/W | DFN 1mmX1mm-4L (NOTE2) | 7 |
| Junction-to-case(bottom) thermal resistance | RθJC(bot) |  | 118 |  | °C/W | DFN 1mmX1mm-4L, JEDEC 2S2P (NOTE2) | 7 |

## Materials and finish

As the datasheet states them (page.json `metadata.appearance`; the 3D model's colours follow it).

| Part | Material | Colour / plating | Datasheet says | Page |
|---|---|---|---|---|
| contacts | copper |  | to IN and OUT pins respectively. Avoid connecting device and chip pins with two different layers of copper, | 18 |

## CAD (KiCad official)

- Symbol: `AW37030D280DNR`
- Footprint: `Package_DFN_QFN:UDFN-4-1EP_1x1mm_P0.65mm_EP0.48x0.48mm`
- 3D model: DFN1x1-4L (KiCad packages3D, STEP)
- 3D model files: `aw37030d280dnr-etched.step` / `aw37030d280dnr-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `aw37030d280dnr.step` / `aw37030d280dnr.glb` are the bare package body.

## Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

- **Datasheet:** [AWINIC Shanghai Awinic Tech datasheet](https://jlcpcb.com/api/file/downloadByFileSystemAccessId/8590440882802892800) (27 pp, sha256 `1e6900a279a56b96`, retrieved 2026-10-20, tier: lcsc)
- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.3`, primary `claude-haiku-5-5` (text), consensus `claude-sonnet-5-5` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
- **CAD:** KiCad official libraries (CC-BY-SA 4.0).

[Datasheet PDF](docs/aw37030d280dnr-datasheet.pdf)