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AVR64EA32-I

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Microchip Tech Microcontrollers (MCU/MPU/SOC), VQFN-32(5x5). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

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AVR64EA32-I

Microchip Tech · Microcontrollers (MCU/MPU/SOC) · VQFN-32(5x5)

AVR64EA32-I from Microchip Tech, in a VQFN-32(5x5). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 PA3 bidirectional General-purpose I/O pin PA3 on the VDD power domain, with analog input AIN23 and alternate functions USART0 XDIR, USART0 RxD (alternate position), TWI0 SCL, TCA0 WO3, CCL LUT0 OUT and EVSYS.
2 PA4 bidirectional General-purpose I/O pin PA4 on the VDD power domain, with analog input AIN24 and alternate functions USART0 TxD (alternate position), SPI0 MOSI, TCA0 WO4 and TCA0 WO0 (alternate position).
3 PA5 bidirectional General-purpose I/O pin PA5 on the VDD power domain, with analog input AIN25 and alternate functions USART0 RxD (alternate position), SPI0 MISO, TCA0 WO5 and TCA0 WO1 (alternate position).
4 PA6 bidirectional General-purpose I/O pin PA6 on the VDD power domain, with analog input AIN26 and alternate functions USART0 XCK (alternate position), SPI0 SCK, TCA0 WO2 (alternate position) and CCL LUT0 OUT (alternate position).
5 PA7 bidirectional General-purpose I/O pin PA7 on the VDD power domain, with analog input AIN27 and alternate functions CLKOUT, AC0/AC1 OUT, USART0 XDIR (alternate position), SPI0 SS and EVSYS EVOUTA (alternate position).
6 PC0 bidirectional General-purpose I/O pin PC0 on the VDD power domain, with analog input AIN28 and alternate functions USART1 TxD, SPI0 SCK/MOSI (alternate positions), TCA0 WO0 (alternate position), TCB0 WO and CCL LUT1 IN0.
7 PC1 bidirectional General-purpose I/O pin PC1 on the VDD power domain, with analog input AIN29 and alternate functions USART1 RxD, USART0 TxD/SS/MISO/MOSI (alternate positions), TCA0 WO1 (alternate position), TCB1 WO and CCL LUT1 IN1.
8 PC2 bidirectional General-purpose I/O pin PC2 on the VDD power domain, with analog input AIN30 and alternate functions AC0 AINN3, USART1 XCK, SPI0 MISO/SCK (alternate positions), TWI0 SDA and CCL LUT1 IN2 with EVSYS EVOUTC.
9 PC3 bidirectional General-purpose I/O pin PC3 on the VDD power domain, with analog input AIN31 and alternate functions AC0 AINP4, USART1 XDIR, SPI0 SS/SCK (alternate positions), TWI0 SCL and CCL LUT1 OUT.
10 PD0 bidirectional General-purpose I/O pin PD0 on the VDD power domain, with analog input AIN0 and alternate functions AC0 AINN1, TCA0 WO0 (alternate position) and CCL LUT2 IN0.
11 PD1 bidirectional General-purpose I/O pin PD1 on the VDD power domain, with analog input AIN1 and alternate functions TCA0 WO1 (alternate position) and CCL LUT2 IN1.
12 PD2 bidirectional General-purpose I/O pin PD2 on the VDD power domain, with analog input AIN2 and alternate functions AC0 AINP0, TCA0 WO2 (alternate position), CCL LUT2 IN2 and EVSYS EVOUTD.
13 PD3 bidirectional General-purpose I/O pin PD3 on the VDD power domain, with analog input AIN3 and alternate functions AC0 AINN0, AC0 AINP1, TCA0 WO3 (alternate position) and CCL LUT2 OUT.
14 PD4 bidirectional General-purpose I/O pin PD4 on the VDD power domain, with analog input AIN4 and alternate functions AC0 AINP2, USART0 TxD/SPI0 MOSI (alternate positions), TCA0 WO4 (alternate position) and TCA0 WO0 (alternate position).
15 PD5 bidirectional General-purpose I/O pin PD5 on the VDD power domain, with analog input AIN5 and alternate functions AC0 AINN0, USART0 RxD/SPI0 MISO (alternate positions), TCA0 WO5 (alternate position) and TCA0 WO1 (alternate position).
16 PD6 bidirectional General-purpose I/O pin PD6 on the VDD power domain, with analog input AIN6 and alternate functions AC0 AINP3, AC0 OUT, USART0 XCK/TxD (alternate positions), SPI0 SCK (alternate position), TCA0 WO2 (alternate position) and CCL LUT2 OUT (alternate position).
17 PD7 bidirectional General-purpose I/O pin PD7 on the VDD power domain, with analog input AIN7, the VREFA external reference alternate function, AC0 AINN2, USART0 XDIR/RxD (alternate positions), SPI0 SS (alternate position) and EVSYS EVOUTD (alternate position).
18 VDD power_in Power supply pin; the same voltage must be applied to all VDD pins, and it powers the I/O lines, XOSCHF and the internal voltage regulator.
19 GND power_in Ground pin; all GND pins must be connected to the same ground plane.
20 PF0 bidirectional General-purpose I/O pin PF0 with 32 kHz crystal function XTAL32K1 and analog input AIN16, plus alternate functions USART2 TxD, TCA0 WO0 (alternate position) and CCL LUT3 IN0.
21 PF1 bidirectional General-purpose I/O pin PF1 with 32 kHz crystal function XTAL32K2 and analog input AIN17, plus alternate functions USART2 RxD, TCA0 WO1 (alternate position) and CCL LUT3 IN1.
22 PF2 bidirectional General-purpose I/O pin PF2 with analog input AIN18 and alternate functions USART2 XCK, TCA0 WO2 (alternate position), CCL LUT3 IN2 and EVSYS EVOUTF.
23 PF3 bidirectional General-purpose I/O pin PF3 with analog input AIN19 and alternate functions USART2 XDIR, TCA0 WO3 (alternate position) and CCL LUT3 OUT.
24 PF4 bidirectional General-purpose I/O pin PF4 with analog input AIN20 and alternate functions USART2 TxD (alternate position) and TCA0 WO4 (alternate position).
25 PF5 bidirectional General-purpose I/O pin PF5 with analog input AIN21 and alternate functions USART2 RxD (alternate position) and TCA0 WO5 (alternate position).
26 PF6 input Pin PF6 is the RESET pin by default (RESET/HV) and is configured as external reset with pull-up when RSTPINCFG is set to RESET, otherwise as an input pin.
27 PF7 bidirectional Pin PF7 is the UPDI programming and debug pin, configured as UPDI with pull-up when UPDIPINCFG is set to UPDI, otherwise a general-purpose I/O pin, with alternate functions TCA0 SS and EVSYS EVOUTF (alternate position).
28 VDD power_in Power supply pin; the same voltage must be applied to all VDD pins, and it powers the I/O lines, XOSCHF and the internal voltage regulator.
29 GND power_in Ground pin; all GND pins must be connected to the same ground plane.
30 PA0 bidirectional General-purpose I/O pin PA0 with high-frequency crystal function XTALHF1 and external clock EXTCLK, plus alternate functions USART0 TxD, SPI0 MOSI, TWI0 SDA, TCA0 WO0, CCL LUT0 IN0 and VDD power domain I/O.
31 PA1 bidirectional General-purpose I/O pin PA1 with high-frequency crystal function XTALHF2, plus alternate functions USART0 RxD, SPI0 MISO, TWI0 SCL, TCA0 WO1 and CCL LUT0 IN1.
32 PA2 bidirectional General-purpose I/O pin PA2 with analog input AIN22, plus alternate functions USART0 XCK, USART0 TxD (alternate position), TWI0 SDA, TCA0 WO2, CCL LUT0 IN2 and EVSYS EVOUTA.
33 EP passive Exposed pad (from the footprint; not named in the datasheet pin table).

Key specifications

Parameter Value
Manufacturer Microchip Tech
Package VQFN-32(5x5)
Category Embedded Processors & Controllers
Pins 33

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
Supply voltage 1.8 5.5 V Ordering table, AVR64EA32-I/RXB VQFN 32-pin 526
Operating temperature range -40 85 °C Ordering table, AVR64EA32-I/RXB VQFN 32-pin 526

CAD (KiCad official)

  • Symbol: AVR64EA32-I
  • Footprint: Package_DFN_QFN:QFN-32-1EP_5x5mm_P0.5mm_EP3.3x3.3mm
  • 3D model: VQFN-32(5x5) (KiCad packages3D, STEP)
  • 3D model files: avr64ea32-i-etched.step / avr64ea32-i-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); avr64ea32-i.step / avr64ea32-i.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Microchip Tech datasheet (565 pp, sha256 1a38a4e7aeeb9404, retrieved 2026-10-28, tier: manufacturer)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF